JESD204B Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683530
Date 10/14/2022
Public
Document Table of Contents
Document Table of Contents x
1. About the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide 2. JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Compiling and Testing the Design 4. Detailed Description for the JESD204B Design Example 5. JESD204B Intel® Agilex™ FPGA IP Design Example User Guide Archives 6. Document Revision History for the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
2. JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.4. Compiling and Simulating the Design x
2.4.1. Testbench
4. Detailed Description for the JESD204B Design Example x
4.1. Presets 4.2. Supported Configurations 4.3. System Components 4.4. Design Example Clock and Reset 4.5. Design Example Signals 4.6. JESD204B Design Example Status and Control Registers 4.7. Hardware Test for System Console Control Design Example
4.3. System Components x
4.3.1. JESD204B Subsystem in Platform Designer 4.3.2. Parallel I/O 4.3.3. Core PLL 4.3.4. SPI Master 4.3.5. Transport Layer 4.3.6. Test Pattern Generator 4.3.7. Test Pattern Checker
4.7. Hardware Test for System Console Control Design Example x
4.7.1. Board Connectivity
1. About the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
2. JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Compiling and Testing the Design
4. Detailed Description for the JESD204B Design Example
5. JESD204B Intel® Agilex™ FPGA IP Design Example User Guide Archives
6. Document Revision History for the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide

4.3.5. Transport Layer

The transport layer in the design example consists of an assembler at the TX path and a deassembler at the RX path. The transport layer for both the TX and RX path is instantiated in the top level RTL file, not in the Platform Designer project.

Note: When the simplex TX data path option is selected, only the assembler is instantiated in the design example. When the simplex RX data path option is selected, only the deassembler is instantiated in the design example. When the duplex data path option is selected, both assembler and deassembler is instantiated in the design example.

The transport layer provides the following services to the application layer (AL) and the data link layer (DLL):

  • Assembler at the TX path:
    • Maps the conversion samples from the AL (through the Avalon® streaming interface) to a specific format of non-scrambled octets, before streaming them to the DLL.
    • Reports AL error to the DLL if it encounters a specific error condition on the Avalon® streaming interface during TX data streaming.
  • Deassembler at the RX path:
    • Maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL (through the Avalon® streaming interface).
    • Reports AL error to the DLL if it encounters a specific error condition on the Avalon® streaming interface during RX data streaming.

The transport layer has many customization options and you can modify the transport layer RTL to customize it to your specifications. Furthermore, for certain parameters like L, F, and N, the transport layer shares the CSR values with the JESD204B IP core.

For more details on the implementation of the transport layer in RTL and customization options, refer to the JESD204B Intel® FPGA IP User Guide.

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