JESD204B Intel® Agilex™ FPGA IP Design Example User Guide

Download PDF
ID 683530
Date 10/14/2022
Public
Document Table of Contents
Document Table of Contents x
1. About the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide 2. JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Compiling and Testing the Design 4. Detailed Description for the JESD204B Design Example 5. JESD204B Intel® Agilex™ FPGA IP Design Example User Guide Archives 6. Document Revision History for the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
2. JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.4. Compiling and Simulating the Design x
2.4.1. Testbench
4. Detailed Description for the JESD204B Design Example x
4.1. Presets 4.2. Supported Configurations 4.3. System Components 4.4. Design Example Clock and Reset 4.5. Design Example Signals 4.6. JESD204B Design Example Status and Control Registers 4.7. Hardware Test for System Console Control Design Example
4.3. System Components x
4.3.1. JESD204B Subsystem in Platform Designer 4.3.2. Parallel I/O 4.3.3. Core PLL Frame Clock and Link Clock Relationship 4.3.4. SPI Master 4.3.5. Transport Layer 4.3.6. Test Pattern Generator 4.3.7. Test Pattern Checker
4.7. Hardware Test for System Console Control Design Example x
4.7.1. Board Connectivity
1. About the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
2. JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Compiling and Testing the Design
4. Detailed Description for the JESD204B Design Example
5. JESD204B Intel® Agilex™ FPGA IP Design Example User Guide Archives
6. Document Revision History for the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide

4.3.3. Core PLL

The core PLL module generates the clocks for the FPGA core fabric. An IOPLL module is instantiated as core PLL.

The core PLL uses an external clock input as its reference clock to generate two derivative clocks from a single VCO:

  • Link clock
  • Frame clock
Table 14.  Core PLL Ouputs
Clock Formula Description
Link Clock Serial data rate/40 The link clock clocks the JESD204B IP core link layer and the link interface of the transport layer.
Frame Clock Derived based on settings; refer to Table 15. The frame clock clocks the transport layer, test pattern generators and checkers, and any downstream modules in the FPGA core fabric.

For the frame clock, when the F parameter is 1, 2 or 3, the resulting frame clock frequency easily exceeds the capability of the core PLL to generate and close timing. The top level RTL file, (altera_jesd204_ed_<data path>.sv), defines the frame clock division factor parameters, F1_FRAMECLK_DIV (for cases with F = 1) and F2_FRAMECLK_DIV (for cases with F = 2). F = 3 uses a constant division factor of 2. This factor enables the transport layer and test pattern generator to operate at a divided factor of the required frame clock rate by widening the data width accordingly.

Note: For JESD204B IP design examples, F1_FRAMECLK_DIV is set to 4 and F2_FRAMECLK_DIV is set to 2.

These examples show how to derive the frame clock frequency:

Example 1: The actual frame clock for a serial data rate of 10 Gbps and F = 1 is: 

(10000/(10 × 1)) / F1_FRAMECLK_DIV = 1000 / 4 = 250 MHz

Example 2: The actual frame clock for a serial data rate of 6 Gbps and F = 3 is: 

(6000/(10 × 3)) / 2 = 200 / 2 = 100 MHz

Frame Clock and Link Clock Relationship

The frame clock and link clock are synchronous. For the derived F mode, the ratio of link_clk period to frame_clk period is given by this formula: 

link_clk period to frame_clk period ratio = 32xL/(MxSxN')
Table 15.  fTXframe and fRXframe for Different F Parameter Settings
  • fTXlink is the TX link clock frequency
  • fRXlink is the RX link clock frequency
F Parameter fTXframe(txframe_clk frequency) fRXframe(rxframe_clk frequency)
1 fTXlinkx(4/F1_FRAMECLK_DIV) fRXlinkx(4/F1_FRAMECLK_DIV)
2 fTXlinkx(2/F2_FRAMECLK_DIV) fRXlinkx(2/F2_FRAMECLK_DIV)
3 fTXlinkx(2/3) fRXlinkx(2/3)
4 fTXlink fRXlink
8 fTXlink/2 fRXlink/2
Note: The IOPLL is generated with the Use Nondedicated Feedback Path option being disabled (default setting). You can turn on the Use Nondedicated Feedback Path option in the IP parameter editor to utilize the clock resources efficiently after the design example is successfully generated. Refer to the Clock Feedback Modes section of Intel® Stratix® 10 Clocking and PLL User Guide for more information about this option.
Related Information
Level Two Title