JESD204B Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683530
Date 10/14/2022
Public
Document Table of Contents
Document Table of Contents x
1. About the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide 2. JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Compiling and Testing the Design 4. Detailed Description for the JESD204B Design Example 5. JESD204B Intel® Agilex™ FPGA IP Design Example User Guide Archives 6. Document Revision History for the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
2. JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.4. Compiling and Simulating the Design x
2.4.1. Testbench
4. Detailed Description for the JESD204B Design Example x
4.1. Presets 4.2. Supported Configurations 4.3. System Components 4.4. Design Example Clock and Reset 4.5. Design Example Signals 4.6. JESD204B Design Example Status and Control Registers 4.7. Hardware Test for System Console Control Design Example
4.3. System Components x
4.3.1. JESD204B Subsystem in Platform Designer 4.3.2. Parallel I/O 4.3.3. Core PLL 4.3.4. SPI Master 4.3.5. Transport Layer 4.3.6. Test Pattern Generator 4.3.7. Test Pattern Checker
4.7. Hardware Test for System Console Control Design Example x
4.7.1. Board Connectivity
1. About the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
2. JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Compiling and Testing the Design
4. Detailed Description for the JESD204B Design Example
5. JESD204B Intel® Agilex™ FPGA IP Design Example User Guide Archives
6. Document Revision History for the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide

2.3.1. Design Example Parameters

The JESD204B Intel® FPGA IP parameter editor includes a Design Example tab for you to specify certain parameters before generating the design example.
Table 5.  Parameters in the Example Design Tab
Parameter Options Description
Available Example Designs None (Default) No design examples selected.
System Console Control Design example with System Console control.
Example Design Files Simulation Generate simulation fileset.
Synthesis Generate synthesis fileset.
Generated HDL Format for Simulation Verilog (Default) Verilog HDL format for entire simulation fileset.
VHDL VHDL format for generated top-level wrapper file set.
Generated HDL Format for Synthesis Verilog (Default) Verilog HDL format for synthesis fileset.
Example Design Customizations Generate 3-wire SPI module Turn on to enable 3-wire SPI interface instead of 4-wire SPI interface.
Target Development Kit None (Default)

This option excludes hardware aspects for the design example. All the pin assignments will be set to virtual pins.

Agilex Signal Integrity Development Kit

This option automatically selects the project’s target device to match the device on this

development kit. All the pin assignments are set according to the development kit.

Level Two Title