AN 832: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel Stratix 10 Devices

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ID 683529
Date 5/24/2018
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Document Table of Contents
Document Table of Contents x
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 832: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization (ILA)
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices

1.6. Test Result Comments

In each test case, the JESD204B receiver IP core successfully initialize from CGS phase, ILA phase, and until user data phase.

No data integrity issue is observed by the PRBS and Ramp checker for all JESD configurations.

In the deterministic latency measurement, consistent total latency is observed across multiple power cycles or resets.

For a few JESD configurations, to avoid lane de-skew error or achieve deterministic latency on FPGA, RBD offset/lmfc offset register needs to be programmed. The modes and the corresponding values used are tabled below.

Mode (LMF) csr_rbd_offset (syncn_sysref_ctrl [10:3]) csr_lmfc_offset

(syncn_sysref_ctrl [19:12])
114-K32 0x2 —
222-K16 0x7 —
222-K32 0x1 —
244-K16 0x1 —
288-K16 0x1 0x1
288-K32 0x1 —
412-K32 0xF —
421-K20 — 0x1
421-K32 0x1 —
422-K16 0x1 —
484-K16 0x1 —
811-K32 – SCR 0 0x6 —
812_K16 0x7 —
812-K32 0xF —
821-K20 0x1 0x1
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