AN 832: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel Stratix 10 Devices

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ID 683529
Date 5/24/2018
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Document Table of Contents
Document Table of Contents x
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 832: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization (ILA)
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices

1.2. Hardware Setup

An Intel® Stratix® 10 GX H-Tile FPGA Development Kit (ES Edition) is used with the ADI AD9208 daughter card module installed to the development board’s FMC connector.

  • The AD9208 EVM derives power from FMC pins.
  • The FPGA device clock is supplied by Si5341 and the sampling clock to the ADC AD9208 EVM is given by external clock source ADF4355.
  • The ADF4355 derives reference clock from the FPGA fPLL. This fPLL derives the reference clock from the device_clk which is supplied by the Si5341 clock generator.
  • For Subclass 1, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9208 device.
  • SYSREF is provided to the ADC through SMA connector.
    Note: Intel® recommends the SYSREF to be provided by the clock generator that sources the device_clk to FPGA and sampling clock to ADC.
Figure 1. Hardware Setup

The following system-level diagram shows how the different modules connect in this design.

Figure 2. System Diagram

In this setup, where LMF = 882, the data rate of transceiver lanes is 16.0 Gbps. An external clock source card provides 400 MHz clock to the FPGA and 1600 MHz sampling clock to AD9208 device. A periodic SYSREF is generated by the FPGA and provided to the ADC through the SMA connector. The JESD204B IP core is instantiated in Duplex mode but only the receiver path is used.

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