AN 832: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel Stratix 10 Devices

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ID 683529
Date 5/24/2018
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Document Table of Contents
Document Table of Contents x
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 832: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization (ILA)
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices

1.4. JESD204B IP Core and ADC Configurations

The JESD204B IP Core parameters (L, M, and F) in this hardware checkout are natively supported by the AD9208 device's quick configuration register at address 0x570. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9208 operating conditions.

The hardware checkout testing implements the JESD204B IP Core with the following parameter configuration.

Global setting for all configuration:

  • N' = 16
  • CS = 0
  • CF = 0
  • Subclass = 1
  • FPGA Management Clock (MHz) = 100
  • Character Replacement = Enabled
  • PCS Option = Soft PCS
Table 6.  Parameter Configuration
LMF HD S N ADC Sampling Clock (MHz) FPGA Device Clock (MHz) 3 FPGA Link Clock (MHz) 4 FPGA Frame Clock (MHz) 4 Lane Rate (Gbps) DDC Enabled Decimation Factor Data Pattern
112 0 1 14 800 400 400 400 16.0 No 1 PRBS-9 Ramp
114 0 2 14 800 400 400 400 16.0 No 1 PRBS-9 Ramp
211 1 1 14 1600 400 400 400 16.0 No 1 PRBS-9 Ramp
212 0 2 14 1600 400 400 400 16.0 No 1 PRBS-9 Ramp
411 1 2 14 3000 375 375 375 15.0 No 1 PRBS-9 Ramp
412 0 4 14 3000 375 375 375 15.0 No 1 PRBS-9 Ramp
811 1 4 14 3000 187.5 187.5 187.5 7.5 No 1 PRBS-9 Ramp
812 0 8 14 3000 187.5 187.5 187.5 7.5 No 1 PRBS-9 Ramp
124 0 1 14 400 400 400 400 16.0 No 1 PRBS-9 Ramp
128 0 2 14 400 400 400 200 16.0 No 1 PRBS-9 Ramp
222 0 1 14 800 400 400 400 16.0 No 1 PRBS-9 Ramp
224 0 2 14 800 400 400 400 16.0 No 1 PRBS-9 Ramp
421 1 1 14 1600 400 400 400 16.0 No 1 PRBS-9 Ramp
422 0 2 14 1600 400 400 400 16.0 No 1 PRBS-9 Ramp
821 1 2 14 3000 375 375 375 15.0 No 1 PRBS-9 Ramp
822 0 4 14 3000 375 375 375 15.0 No 1 PRBS-9 Ramp
148 0 1 16 400 400 400 200 16.0 Yes 2 PRBS-9 Ramp
244 0 1 16 800 400 400 400 16.0 Yes 2 PRBS-9 Ramp
248 0 2 16 800 400 400 200 16.0 Yes 2 PRBS-9 Ramp
442 0 1 16 1600 400 400 400 16.0 Yes 2 PRBS-9 Ramp
444 0 2 16 1600 400 400 400 16.0 Yes 2 PRBS-9 Ramp
841 1 1 16 3000 375 375 400 15.0 Yes 2 PRBS-9 Ramp
842 0 2 16 3000 375 375 400 15.0 Yes 2 PRBS-9 Ramp
288 0 1 16 400 400 400 200 16.0 Yes 2 PRBS-9 Ramp
484 0 1 16 800 400 400 400 16.0 Yes 2 PRBS-9 Ramp
488 0 2 16 800 400 400 200 16.0 Yes 2 PRBS-9 Ramp
882 0 1 16 1600 400 400 400 16.0 Yes 2 PRBS-9 Ramp
884 0 2 16 1600 400 400 400 16.0 Yes 2 PRBS-9 Ramp
3 The device clock is used to clock the transceiver.
4 The frame clock and link clock are derived from the device clock using an internal PLL.
Level Two Title