Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

Download PDF
ID 683527
Date 10/19/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Introduction 2. Quick Start Guide 3. Block and Interface Descriptions 4. Parameters 5. Designing with the IP Core 6. Registers 7. Design Example and Testbench A. Troubleshooting and Observing the Link B. Avalon-MM IP Variants Comparison C. Root Port BFM D. BFM Procedures and Functions E. Root Port Enumeration F. Document Revision History for Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Release Information 1.4. Recommended Speed Grades 1.5. Resource Utilization 1.6. Transceiver Tiles 1.7. Channel Availability
2. Quick Start Guide x
2.1. Design Components 2.2. Directory Structure 2.3. Generating the Design Example 2.4. Simulating the Design Example 2.5. Compiling the Design Example and Programming the Device 2.6. Installing the Linux Kernel Driver 2.7. Running the Design Example Application 2.8. Ensuring the Design Example Meets Timing Requirements
3. Block and Interface Descriptions x
3.1. Block Descriptions 3.2. Interface Descriptions
3.1. Block Descriptions x
3.1.1. Tags
3.2. Interface Descriptions x
3.2.1. Avalon-MM Interface Summary 3.2.2. Clocks and Resets 3.2.3. System Interfaces
3.2.1. Avalon-MM Interface Summary x
3.2.1.1. Read Data Mover (RDDM) Interfaces 3.2.1.2. Write Data Mover (WRDM) Interfaces 3.2.1.3. Bursting Avalon-MM Slave (BAS) Interface 3.2.1.4. Bursting Avalon-MM Master (BAM) Interface
3.2.1.1. Read Data Mover (RDDM) Interfaces x
3.2.1.1.1. Read Data Mover Avalon-MM Write Master and Conduit 3.2.1.1.2. Read Data Mover Avalon-ST Descriptor Sinks 3.2.1.1.3. Read Data Mover Status Avalon-ST Source
3.2.1.2. Write Data Mover (WRDM) Interfaces x
3.2.1.2.1. Write Data Mover Avalon-MM Read Master and Conduit 3.2.1.2.2. Write Data Mover Avalon-ST Descriptor Sinks 3.2.1.2.3. Write Data Mover Status Avalon-ST Source
3.2.1.4. Bursting Avalon-MM Master (BAM) Interface x
3.2.1.4.1. PCIe Address to Avalon-MM Address Mapping
3.2.3. System Interfaces x
3.2.3.1. Serial Data Interface 3.2.3.2. PIPE Interface 3.2.3.3. Interrupts 3.2.3.4. Configuration Output Interface 3.2.3.5. Flush Requests 3.2.3.6. Reconfiguration 3.2.3.7. Hard IP Status and Link Training Conduit 3.2.3.8. Bus Master Enable (BME) Conduit 3.2.3.9. Test Conduit
3.2.3.3. Interrupts x
3.2.3.3.1. Interrupt Signals Available when the PCIe Hard IP is an Endpoint 3.2.3.3.2. MSI
3.2.3.6. Reconfiguration x
3.2.3.6.1. PCIe Hard IP Reconfiguration 3.2.3.6.2. Transceiver Reconfiguration 3.2.3.6.3. PLL Reconfiguration
4. Parameters x
4.1. Avalon-MM Settings 4.2. Base Address Registers 4.3. Device Identification Registers 4.4. PCI Express and PCI Capabilities Parameters 4.5. Configuration, Debug and Extension Options 4.6. PHY Characteristics 4.7. Example Designs
4.4. PCI Express and PCI Capabilities Parameters x
4.4.1. Device Capabilities 4.4.2. Link Capabilities 4.4.3. MSI and MSI-X Capabilities 4.4.4. Power Management 4.4.5. Vendor Specific Extended Capability (VSEC)
5. Designing with the IP Core x
5.1. Generation 5.2. Simulation 5.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.4. Channel Layout and PLL Usage
6. Registers x
6.1. Configuration Space Registers
6.1. Configuration Space Registers x
6.1.1. Register Access Definitions 6.1.2. PCI Configuration Header Registers 6.1.3. PCI Express Capability Structures 6.1.4. Intel Defined VSEC Capability Header 6.1.5. Uncorrectable Internal Error Status Register 6.1.6. Uncorrectable Internal Error Mask Register 6.1.7. Correctable Internal Error Status Register 6.1.8. Correctable Internal Error Mask Register
6.1.4. Intel Defined VSEC Capability Header x
6.1.4.1. Intel Defined Vendor Specific Header 6.1.4.2. Intel Marker 6.1.4.3. JTAG Silicon ID 6.1.4.4. User Configurable Device and Board ID
7. Design Example and Testbench x
7.1. Overview of the Example Design 7.2. Overview of the Testbench
7.1. Overview of the Example Design x
7.1.1. Block Descriptions 7.1.2. Programming Model for the Example Design 7.1.3. DMA Operations Using the Example Design
7.1.1. Block Descriptions x
7.1.1.1. DMA Controller (DMA Example Design Only) 7.1.1.2. Traffic Generator and Checker (BAS Example Design Only) 7.1.1.3. Avalon-MM Address to PCIe Address Mapping 7.1.1.4. BAR Interpreter
7.1.1.1. DMA Controller (DMA Example Design Only) x
7.1.1.1.1. Register Set 7.1.1.1.2. Deadlock Risk and Avoidance 7.1.1.1.3. Interrupts 7.1.1.1.4. Using the DMA Controller
7.1.1.2. Traffic Generator and Checker (BAS Example Design Only) x
7.1.1.2.1. Register Set
7.1.3. DMA Operations Using the Example Design x
7.1.3.1. Read DMA Example 7.1.3.2. Write DMA Example 7.1.3.3. Using the Traffic Generator (BAS Example Design Only) 7.1.3.4. Using the Traffic Checker (BAS Example Design Only)
A. Troubleshooting and Observing the Link x
A.1. Troubleshooting A.2. PCIe Link Inspector Overview
A.1. Troubleshooting x
A.1.1. Simulation Fails to Progress Beyond Polling.Active State A.1.2. Hardware Bring-Up Issues A.1.3. Link Training A.1.4. Use Third-Party PCIe Analyzer
A.2. PCIe Link Inspector Overview x
A.2.1. PCIe* Link Inspector Hardware
A.2.1. PCIe* Link Inspector Hardware x
A.2.1.1. Enabling the PCIe* Link Inspector A.2.1.2. Launching the PCIe* Link Inspector A.2.1.3. The PCIe* Link Inspector LTSSM Monitor A.2.1.4. Accessing the Configuration Space and Transceiver Registers A.2.1.5. Additional Status Commands
A.2.1.3. The PCIe* Link Inspector LTSSM Monitor x
A.2.1.3.1. LTSSM Monitor Registers A.2.1.3.2. ltssm_save2file <file_name> A.2.1.3.3. ltssm_file2console A.2.1.3.4. ltssm_debug_check A.2.1.3.5. ltssm_display <num_states> A.2.1.3.6. ltssm_save_oldstates
A.2.1.4. Accessing the Configuration Space and Transceiver Registers x
A.2.1.4.1. PCIe* Link Inspector Commands A.2.1.4.2. NPDME PLL and Channel Commands A.2.1.4.3. Register Address Map
A.2.1.5. Additional Status Commands x
A.2.1.5.1. Displaying PLL Lock and Calibration Status Registers
C. Root Port BFM x
C.1. Root Port BFM Overview C.2. Issuing Read and Write Transactions to the Application Layer C.3. Configuration of Root Port and Endpoint C.4. Configuration Space Bus and Device Numbering C.5. BFM Memory Map
D. BFM Procedures and Functions x
D.1. ebfm_barwr Procedure D.2. ebfm_barwr_imm Procedure D.3. ebfm_barrd_wait Procedure D.4. ebfm_barrd_nowt Procedure D.5. ebfm_cfgwr_imm_wait Procedure D.6. ebfm_cfgwr_imm_nowt Procedure D.7. ebfm_cfgrd_wait Procedure D.8. ebfm_cfgrd_nowt Procedure D.9. BFM Configuration Procedures D.10. BFM Shared Memory Access Procedures D.11. BFM Log and Message Procedures D.12. Verilog HDL Formatting Functions
D.9. BFM Configuration Procedures x
D.9.1. ebfm_cfg_rp_ep Procedure D.9.2. ebfm_cfg_decode_bar Procedure
D.10. BFM Shared Memory Access Procedures x
D.10.1. Shared Memory Constants D.10.2. shmem_write Procedure D.10.3. shmem_read Function D.10.4. shmem_display Verilog HDL Function D.10.5. shmem_fill Procedure D.10.6. shmem_chk_ok Function
D.11. BFM Log and Message Procedures x
D.11.1. ebfm_display Verilog HDL Function D.11.2. ebfm_log_stop_sim Verilog HDL Function D.11.3. ebfm_log_set_suppressed_msg_mask Task D.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task D.11.5. ebfm_log_open Verilog HDL Function D.11.6. ebfm_log_close Verilog HDL Function
D.12. Verilog HDL Formatting Functions x
D.12.1. himage1 D.12.2. himage2 D.12.3. himage4 D.12.4. himage8 D.12.5. himage16 D.12.6. dimage1 D.12.7. dimage2 D.12.8. dimage3 D.12.9. dimage4 D.12.10. dimage5 D.12.11. dimage6 D.12.12. dimage7
1. Introduction
2. Quick Start Guide
3. Block and Interface Descriptions
4. Parameters
5. Designing with the IP Core
6. Registers
7. Design Example and Testbench
A. Troubleshooting and Observing the Link
B. Avalon-MM IP Variants Comparison
C. Root Port BFM
D. BFM Procedures and Functions
E. Root Port Enumeration
F. Document Revision History for Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

C.1. Root Port BFM Overview

The basic Root Port BFM provides a Verilog HDL task‑based interface to test the PCIe* link. The Root Port BFM also handles requests received from the PCIe* link. The following figure provides an overview of the Root Port BFM.

Figure 35. Root Port BFM

The following descriptions provides an overview of the blocks shown in the Root Port BFM figure:

  • BFM shared memory (altpcietb_g3bfm_shmem.v): The BFM memory performs the following tasks:
      • Stores data received with all completions from the PCI Express link.
      • Stores data received with all write transactions received from the PCI Express link.
      • Sources data for all completions in response to read transactions received from the PCI Express* link.
      • Sources data for most write transactions issued to the link. The only exception is certain BFM PCI Express* write procedures that have a four-byte field of write data passed in the call.
      • Stores a data structure that contains the sizes of and the values programmed in the BARs of the Endpoint.

A set of procedures read, write, fill, and check the shared memory from the BFM driver. For details on these procedures, see BFM Shared Memory Access Procedures.

  • BFM Read/Write Request Functions (altpcietb_g3bfm_rdwr.v): These functions provide the basic BFM calls for PCI Express* read and write requests. For details on these procedures, refer to BFM Read and Write Procedures.
  • BFM Configuration Functions (altpcietb_g3bfm_rp.v ): These functions provide the BFM calls to request configuration of the PCI Express* link and the Endpoint Configuration Space registers. For details on these procedures and functions, refer to BFM Configuration Procedures.
  • BFM Log Interface (altpcietb_g3bfm_log.v): The BFM log functions provides routines for writing commonly formatted messages to the simulator standard output and optionally to a log file. It also provides controls that stop simulation on errors. For details on these procedures, refer to BFM Log and Message Procedures.
  • BFM Request Interface (altpcietb_g3bfm_req_intf.v): This interface provides the low-level interface between the altpcietb_g3bfm_rdwr.v and altpcietb_g3bfm_configure.v procedures or functions and the Root Port RTL Model. This interface stores a write-protected data structure containing the sizes and the values programmed in the BAR registers of the Endpoint. This interface also stores other critical data used for internal BFM management. You do not need to access these files directly to adapt the testbench to test your Endpoint application.
  • Avalon‑ST Interfaces (altpcietb_bfm_vc_intf_ast_common.v): These interface modules handle the Root Port interface model. They take requests from the BFM request interface and generate the required PCI Express* transactions. They handle completions received from the PCI Express* link and notify the BFM request interface when requests are complete. Additionally, they handle any requests received from the PCI Express* link, and store or fetch data from the shared memory before generating the required completions.
Level Two Title