Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

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ID 683527
Date 10/19/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Quick Start Guide 3. Block and Interface Descriptions 4. Parameters 5. Designing with the IP Core 6. Registers 7. Design Example and Testbench A. Troubleshooting and Observing the Link B. Avalon-MM IP Variants Comparison C. Root Port BFM D. BFM Procedures and Functions E. Root Port Enumeration F. Document Revision History for Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Release Information 1.4. Recommended Speed Grades 1.5. Resource Utilization 1.6. Transceiver Tiles 1.7. Channel Availability
2. Quick Start Guide x
2.1. Design Components 2.2. Directory Structure 2.3. Generating the Design Example 2.4. Simulating the Design Example 2.5. Compiling the Design Example and Programming the Device 2.6. Installing the Linux Kernel Driver 2.7. Running the Design Example Application 2.8. Ensuring the Design Example Meets Timing Requirements
3. Block and Interface Descriptions x
3.1. Block Descriptions 3.2. Interface Descriptions
3.1. Block Descriptions x
3.1.1. Tags
3.2. Interface Descriptions x
3.2.1. Avalon-MM Interface Summary 3.2.2. Clocks and Resets 3.2.3. System Interfaces
3.2.1. Avalon-MM Interface Summary x
3.2.1.1. Read Data Mover (RDDM) Interfaces 3.2.1.2. Write Data Mover (WRDM) Interfaces 3.2.1.3. Bursting Avalon-MM Slave (BAS) Interface 3.2.1.4. Bursting Avalon-MM Master (BAM) Interface
3.2.1.1. Read Data Mover (RDDM) Interfaces x
3.2.1.1.1. Read Data Mover Avalon-MM Write Master and Conduit 3.2.1.1.2. Read Data Mover Avalon-ST Descriptor Sinks 3.2.1.1.3. Read Data Mover Status Avalon-ST Source
3.2.1.2. Write Data Mover (WRDM) Interfaces x
3.2.1.2.1. Write Data Mover Avalon-MM Read Master and Conduit 3.2.1.2.2. Write Data Mover Avalon-ST Descriptor Sinks 3.2.1.2.3. Write Data Mover Status Avalon-ST Source
3.2.1.4. Bursting Avalon-MM Master (BAM) Interface x
3.2.1.4.1. PCIe Address to Avalon-MM Address Mapping
3.2.3. System Interfaces x
3.2.3.1. Serial Data Interface 3.2.3.2. PIPE Interface 3.2.3.3. Interrupts 3.2.3.4. Configuration Output Interface 3.2.3.5. Flush Requests 3.2.3.6. Reconfiguration 3.2.3.7. Hard IP Status and Link Training Conduit 3.2.3.8. Bus Master Enable (BME) Conduit 3.2.3.9. Test Conduit
3.2.3.3. Interrupts x
3.2.3.3.1. Interrupt Signals Available when the PCIe Hard IP is an Endpoint 3.2.3.3.2. MSI
3.2.3.6. Reconfiguration x
3.2.3.6.1. PCIe Hard IP Reconfiguration 3.2.3.6.2. Transceiver Reconfiguration 3.2.3.6.3. PLL Reconfiguration
4. Parameters x
4.1. Avalon-MM Settings 4.2. Base Address Registers 4.3. Device Identification Registers 4.4. PCI Express and PCI Capabilities Parameters 4.5. Configuration, Debug and Extension Options 4.6. PHY Characteristics 4.7. Example Designs
4.4. PCI Express and PCI Capabilities Parameters x
4.4.1. Device Capabilities 4.4.2. Link Capabilities 4.4.3. MSI and MSI-X Capabilities 4.4.4. Power Management 4.4.5. Vendor Specific Extended Capability (VSEC)
5. Designing with the IP Core x
5.1. Generation 5.2. Simulation 5.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.4. Channel Layout and PLL Usage
6. Registers x
6.1. Configuration Space Registers
6.1. Configuration Space Registers x
6.1.1. Register Access Definitions 6.1.2. PCI Configuration Header Registers 6.1.3. PCI Express Capability Structures 6.1.4. Intel Defined VSEC Capability Header 6.1.5. Uncorrectable Internal Error Status Register 6.1.6. Uncorrectable Internal Error Mask Register 6.1.7. Correctable Internal Error Status Register 6.1.8. Correctable Internal Error Mask Register
6.1.4. Intel Defined VSEC Capability Header x
6.1.4.1. Intel Defined Vendor Specific Header 6.1.4.2. Intel Marker 6.1.4.3. JTAG Silicon ID 6.1.4.4. User Configurable Device and Board ID
7. Design Example and Testbench x
7.1. Overview of the Example Design 7.2. Overview of the Testbench
7.1. Overview of the Example Design x
7.1.1. Block Descriptions 7.1.2. Programming Model for the Example Design 7.1.3. DMA Operations Using the Example Design
7.1.1. Block Descriptions x
7.1.1.1. DMA Controller (DMA Example Design Only) 7.1.1.2. Traffic Generator and Checker (BAS Example Design Only) 7.1.1.3. Avalon-MM Address to PCIe Address Mapping 7.1.1.4. BAR Interpreter
7.1.1.1. DMA Controller (DMA Example Design Only) x
7.1.1.1.1. Register Set 7.1.1.1.2. Deadlock Risk and Avoidance 7.1.1.1.3. Interrupts 7.1.1.1.4. Using the DMA Controller
7.1.1.2. Traffic Generator and Checker (BAS Example Design Only) x
7.1.1.2.1. Register Set
7.1.3. DMA Operations Using the Example Design x
7.1.3.1. Read DMA Example 7.1.3.2. Write DMA Example 7.1.3.3. Using the Traffic Generator (BAS Example Design Only) 7.1.3.4. Using the Traffic Checker (BAS Example Design Only)
A. Troubleshooting and Observing the Link x
A.1. Troubleshooting A.2. PCIe Link Inspector Overview
A.1. Troubleshooting x
A.1.1. Simulation Fails to Progress Beyond Polling.Active State A.1.2. Hardware Bring-Up Issues A.1.3. Link Training A.1.4. Use Third-Party PCIe Analyzer
A.2. PCIe Link Inspector Overview x
A.2.1. PCIe* Link Inspector Hardware
A.2.1. PCIe* Link Inspector Hardware x
A.2.1.1. Enabling the PCIe* Link Inspector A.2.1.2. Launching the PCIe* Link Inspector A.2.1.3. The PCIe* Link Inspector LTSSM Monitor A.2.1.4. Accessing the Configuration Space and Transceiver Registers A.2.1.5. Additional Status Commands
A.2.1.3. The PCIe* Link Inspector LTSSM Monitor x
A.2.1.3.1. LTSSM Monitor Registers A.2.1.3.2. ltssm_save2file <file_name> A.2.1.3.3. ltssm_file2console A.2.1.3.4. ltssm_debug_check A.2.1.3.5. ltssm_display <num_states> A.2.1.3.6. ltssm_save_oldstates
A.2.1.4. Accessing the Configuration Space and Transceiver Registers x
A.2.1.4.1. PCIe* Link Inspector Commands A.2.1.4.2. NPDME PLL and Channel Commands A.2.1.4.3. Register Address Map
A.2.1.5. Additional Status Commands x
A.2.1.5.1. Displaying PLL Lock and Calibration Status Registers
C. Root Port BFM x
C.1. Root Port BFM Overview C.2. Issuing Read and Write Transactions to the Application Layer C.3. Configuration of Root Port and Endpoint C.4. Configuration Space Bus and Device Numbering C.5. BFM Memory Map
D. BFM Procedures and Functions x
D.1. ebfm_barwr Procedure D.2. ebfm_barwr_imm Procedure D.3. ebfm_barrd_wait Procedure D.4. ebfm_barrd_nowt Procedure D.5. ebfm_cfgwr_imm_wait Procedure D.6. ebfm_cfgwr_imm_nowt Procedure D.7. ebfm_cfgrd_wait Procedure D.8. ebfm_cfgrd_nowt Procedure D.9. BFM Configuration Procedures D.10. BFM Shared Memory Access Procedures D.11. BFM Log and Message Procedures D.12. Verilog HDL Formatting Functions
D.9. BFM Configuration Procedures x
D.9.1. ebfm_cfg_rp_ep Procedure D.9.2. ebfm_cfg_decode_bar Procedure
D.10. BFM Shared Memory Access Procedures x
D.10.1. Shared Memory Constants D.10.2. shmem_write Procedure D.10.3. shmem_read Function D.10.4. shmem_display Verilog HDL Function D.10.5. shmem_fill Procedure D.10.6. shmem_chk_ok Function
D.11. BFM Log and Message Procedures x
D.11.1. ebfm_display Verilog HDL Function D.11.2. ebfm_log_stop_sim Verilog HDL Function D.11.3. ebfm_log_set_suppressed_msg_mask Task D.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task D.11.5. ebfm_log_open Verilog HDL Function D.11.6. ebfm_log_close Verilog HDL Function
D.12. Verilog HDL Formatting Functions x
D.12.1. himage1 D.12.2. himage2 D.12.3. himage4 D.12.4. himage8 D.12.5. himage16 D.12.6. dimage1 D.12.7. dimage2 D.12.8. dimage3 D.12.9. dimage4 D.12.10. dimage5 D.12.11. dimage6 D.12.12. dimage7
1. Introduction
2. Quick Start Guide
3. Block and Interface Descriptions
4. Parameters
5. Designing with the IP Core
6. Registers
7. Design Example and Testbench
A. Troubleshooting and Observing the Link
B. Avalon-MM IP Variants Comparison
C. Root Port BFM
D. BFM Procedures and Functions
E. Root Port Enumeration
F. Document Revision History for Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

C.3. Configuration of Root Port and Endpoint

Before you issue transactions to the Endpoint, you must configure the Root Port and Endpoint Configuration Space registers.

The ebfm_cfg_rp_ep procedure executes the following steps to initialize the Configuration Space:

  1. Sets the Root Port Configuration Space to enable the Root Port to send transactions on the PCI Express link.
  2. Sets the Root Port and Endpoint PCI Express Capability Device Control registers as follows:
    1. Disables Error Reporting in both the Root Port and Endpoint. The BFM does not have error handling capability.
    2. Enables Relaxed Ordering in both Root Port and Endpoint.
    3. Enables Extended Tags for the Endpoint if the Endpoint has that capability.
    4. Disables Phantom Functions, Aux Power PM, and No Snoop in both the Root Port and Endpoint.
    5. Sets the Max Payload Size to the value that the Endpoint supports because the Root Port supports the maximum payload size.
    6. Sets the Root Port Max Read Request Size to 4 KB because the example Endpoint design supports breaking the read into as many completions as necessary.
    7. Sets the Endpoint Max Read Request Size equal to the Max Payload Size because the Root Port does not support breaking the read request into multiple completions.
  3. Assigns values to all the Endpoint BAR registers. The BAR addresses are assigned by the algorithm outlined below.
    1. I/O BARs are assigned smallest to largest starting just above the ending address of BFM shared memory in I/O space and continuing as needed throughout a full 32-bit I/O space.
    2. The 32-bit non-prefetchable memory BARs are assigned smallest to largest, starting just above the ending address of BFM shared memory in memory space and continuing as needed throughout a full 32-bit memory space.
    3. The value of the addr_map_4GB_limit input to the ebfm_cfg_rp_ep procedure controls the assignment of the 32-bit prefetchable and 64-bit prefetchable memory BARS. The default value of addr_map_4GB_limit is 0.

      If addr_map_4GB_limit is set to 0, then the ebfm_cfg_rp_ep procedure assigns the 32‑bit prefetchable memory BARs largest to smallest, starting at the top of 32-bit memory space and continuing as needed down to the ending address of the last 32-bit non-prefetchable BAR. When addr_map_4GB_limit is set to 0, the ebfm_cfg_rp_ep procedure also assigns the 64-bit prefetchable memory BARs smallest to largest starting at the 4 GB address assigning memory ascending above the 4 GB limit throughout the full 64-bit memory space.

      However, if addr_map_4GB_limit is set to 1, the address map is limited to 4 GB. The ebfm_cfg_rp_ep procedure assigns 32-bit and 64-bit prefetchable memory BARs largest to smallest, starting at the 4 GB address and continuing as needed down to the ending address of the last 32-bit non-prefetchable BAR.

    4. The above algorithm cannot always assign values to all BARs when there are a few very large (1 GB or greater) 32-bit BARs. Although assigning addresses to all BARs may be possible, a more complex algorithm would be required to effectively assign these addresses. However, such a configuration is unlikely to be useful in real systems. If the procedure is unable to assign the BARs, it displays an error message and stops the simulation.
  4. Based on the above BAR assignments, the ebfm_cfg_rp_ep procedure assigns the Root Port Configuration Space address windows to encompass the valid BAR address ranges.
  5. The ebfm_cfg_rp_ep procedure enables master transactions, memory address decoding, and I/O address decoding in the Endpoint PCIe* control register.

The ebfm_cfg_rp_ep procedure also sets up a bar_table data structure in BFM shared memory that lists the sizes and assigned addresses of all Endpoint BARs. This area of BFM shared memory is write-protected. Consequently, any application logic write accesses to this area cause a fatal simulation error.

BFM procedure calls to generate full PCIe* addresses for read and write requests to particular offsets from a BAR use this data structure. This procedure allows the testbench code that accesses the Endpoint application logic to use offsets from a BAR and avoid tracking specific addresses assigned to the BAR. The following table shows how to use those offsets.

Table 74.  BAR Table Structure

Offset (Bytes)

Description

+0

PCI Express address in BAR0

+4

PCI Express address in BAR1

+8

PCI Express address in BAR2

+12

PCI Express address in BAR3

+16

PCI Express address in BAR4

+20

PCI Express address in BAR5

+24

PCI Express address in Expansion ROM BAR

+28

Reserved

+32

BAR0 read back value after being written with all 1’s (used to compute size)

+36

BAR1 read back value after being written with all 1’s

+40

BAR2 read back value after being written with all 1’s

+44

BAR3 read back value after being written with all 1’s

+48

BAR4 read back value after being written with all 1’s

+52

BAR5 read back value after being written with all 1’s

+56

Expansion ROM BAR read back value after being written with all 1’s

+60

Reserved

The configuration routine does not configure any advanced PCI Express capabilities such as the AER capability.

Besides the ebfm_cfg_rp_ep procedure in altpcietb_bfm_rp_gen3_x8.sv, routines to read and write Endpoint Configuration Space registers directly are available in the Verilog HDL include file. After the ebfm_cfg_rp_ep procedure runs the PCI Express I/O and Memory Spaces have the layout shown in the following three figures. The memory space layout depends on the value of the addr_map_4GB_limit input parameter. The following figure shows the resulting memory space map when the addr_map_4GB_limit is 1.

Figure 36. Memory Space Layout—4 GB Limit

The following figure shows the resulting memory space map when the addr_map_4GB_limit is 0.

Figure 37. Memory Space Layout—No Limit

The following figure shows the I/O address space.

Figure 38. I/O Address Space
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