Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

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ID 683527
Date 10/19/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Quick Start Guide 3. Block and Interface Descriptions 4. Parameters 5. Designing with the IP Core 6. Registers 7. Design Example and Testbench A. Troubleshooting and Observing the Link B. Avalon-MM IP Variants Comparison C. Root Port BFM D. BFM Procedures and Functions E. Root Port Enumeration F. Document Revision History for Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Release Information 1.4. Recommended Speed Grades 1.5. Resource Utilization 1.6. Transceiver Tiles 1.7. Channel Availability
2. Quick Start Guide x
2.1. Design Components 2.2. Directory Structure 2.3. Generating the Design Example 2.4. Simulating the Design Example 2.5. Compiling the Design Example and Programming the Device 2.6. Installing the Linux Kernel Driver 2.7. Running the Design Example Application 2.8. Ensuring the Design Example Meets Timing Requirements
3. Block and Interface Descriptions x
3.1. Block Descriptions 3.2. Interface Descriptions
3.1. Block Descriptions x
3.1.1. Tags
3.2. Interface Descriptions x
3.2.1. Avalon-MM Interface Summary 3.2.2. Clocks and Resets 3.2.3. System Interfaces
3.2.1. Avalon-MM Interface Summary x
3.2.1.1. Read Data Mover (RDDM) Interfaces 3.2.1.2. Write Data Mover (WRDM) Interfaces 3.2.1.3. Bursting Avalon-MM Slave (BAS) Interface 3.2.1.4. Bursting Avalon-MM Master (BAM) Interface
3.2.1.1. Read Data Mover (RDDM) Interfaces x
3.2.1.1.1. Read Data Mover Avalon-MM Write Master and Conduit 3.2.1.1.2. Read Data Mover Avalon-ST Descriptor Sinks 3.2.1.1.3. Read Data Mover Status Avalon-ST Source
3.2.1.2. Write Data Mover (WRDM) Interfaces x
3.2.1.2.1. Write Data Mover Avalon-MM Read Master and Conduit 3.2.1.2.2. Write Data Mover Avalon-ST Descriptor Sinks 3.2.1.2.3. Write Data Mover Status Avalon-ST Source
3.2.1.4. Bursting Avalon-MM Master (BAM) Interface x
3.2.1.4.1. PCIe Address to Avalon-MM Address Mapping
3.2.3. System Interfaces x
3.2.3.1. Serial Data Interface 3.2.3.2. PIPE Interface 3.2.3.3. Interrupts 3.2.3.4. Configuration Output Interface 3.2.3.5. Flush Requests 3.2.3.6. Reconfiguration 3.2.3.7. Hard IP Status and Link Training Conduit 3.2.3.8. Bus Master Enable (BME) Conduit 3.2.3.9. Test Conduit
3.2.3.3. Interrupts x
3.2.3.3.1. Interrupt Signals Available when the PCIe Hard IP is an Endpoint 3.2.3.3.2. MSI
3.2.3.6. Reconfiguration x
3.2.3.6.1. PCIe Hard IP Reconfiguration 3.2.3.6.2. Transceiver Reconfiguration 3.2.3.6.3. PLL Reconfiguration
4. Parameters x
4.1. Avalon-MM Settings 4.2. Base Address Registers 4.3. Device Identification Registers 4.4. PCI Express and PCI Capabilities Parameters 4.5. Configuration, Debug and Extension Options 4.6. PHY Characteristics 4.7. Example Designs
4.4. PCI Express and PCI Capabilities Parameters x
4.4.1. Device Capabilities 4.4.2. Link Capabilities 4.4.3. MSI and MSI-X Capabilities 4.4.4. Power Management 4.4.5. Vendor Specific Extended Capability (VSEC)
5. Designing with the IP Core x
5.1. Generation 5.2. Simulation 5.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.4. Channel Layout and PLL Usage
6. Registers x
6.1. Configuration Space Registers
6.1. Configuration Space Registers x
6.1.1. Register Access Definitions 6.1.2. PCI Configuration Header Registers 6.1.3. PCI Express Capability Structures 6.1.4. Intel Defined VSEC Capability Header 6.1.5. Uncorrectable Internal Error Status Register 6.1.6. Uncorrectable Internal Error Mask Register 6.1.7. Correctable Internal Error Status Register 6.1.8. Correctable Internal Error Mask Register
6.1.4. Intel Defined VSEC Capability Header x
6.1.4.1. Intel Defined Vendor Specific Header 6.1.4.2. Intel Marker 6.1.4.3. JTAG Silicon ID 6.1.4.4. User Configurable Device and Board ID
7. Design Example and Testbench x
7.1. Overview of the Example Design 7.2. Overview of the Testbench
7.1. Overview of the Example Design x
7.1.1. Block Descriptions 7.1.2. Programming Model for the Example Design 7.1.3. DMA Operations Using the Example Design
7.1.1. Block Descriptions x
7.1.1.1. DMA Controller (DMA Example Design Only) 7.1.1.2. Traffic Generator and Checker (BAS Example Design Only) 7.1.1.3. Avalon-MM Address to PCIe Address Mapping 7.1.1.4. BAR Interpreter
7.1.1.1. DMA Controller (DMA Example Design Only) x
7.1.1.1.1. Register Set 7.1.1.1.2. Deadlock Risk and Avoidance 7.1.1.1.3. Interrupts 7.1.1.1.4. Using the DMA Controller
7.1.1.2. Traffic Generator and Checker (BAS Example Design Only) x
7.1.1.2.1. Register Set
7.1.3. DMA Operations Using the Example Design x
7.1.3.1. Read DMA Example 7.1.3.2. Write DMA Example 7.1.3.3. Using the Traffic Generator (BAS Example Design Only) 7.1.3.4. Using the Traffic Checker (BAS Example Design Only)
A. Troubleshooting and Observing the Link x
A.1. Troubleshooting A.2. PCIe Link Inspector Overview
A.1. Troubleshooting x
A.1.1. Simulation Fails to Progress Beyond Polling.Active State A.1.2. Hardware Bring-Up Issues A.1.3. Link Training A.1.4. Use Third-Party PCIe Analyzer
A.2. PCIe Link Inspector Overview x
A.2.1. PCIe* Link Inspector Hardware
A.2.1. PCIe* Link Inspector Hardware x
A.2.1.1. Enabling the PCIe* Link Inspector A.2.1.2. Launching the PCIe* Link Inspector A.2.1.3. The PCIe* Link Inspector LTSSM Monitor A.2.1.4. Accessing the Configuration Space and Transceiver Registers A.2.1.5. Additional Status Commands
A.2.1.3. The PCIe* Link Inspector LTSSM Monitor x
A.2.1.3.1. LTSSM Monitor Registers A.2.1.3.2. ltssm_save2file <file_name> A.2.1.3.3. ltssm_file2console A.2.1.3.4. ltssm_debug_check A.2.1.3.5. ltssm_display <num_states> A.2.1.3.6. ltssm_save_oldstates
A.2.1.4. Accessing the Configuration Space and Transceiver Registers x
A.2.1.4.1. PCIe* Link Inspector Commands A.2.1.4.2. NPDME PLL and Channel Commands A.2.1.4.3. Register Address Map
A.2.1.5. Additional Status Commands x
A.2.1.5.1. Displaying PLL Lock and Calibration Status Registers
C. Root Port BFM x
C.1. Root Port BFM Overview C.2. Issuing Read and Write Transactions to the Application Layer C.3. Configuration of Root Port and Endpoint C.4. Configuration Space Bus and Device Numbering C.5. BFM Memory Map
D. BFM Procedures and Functions x
D.1. ebfm_barwr Procedure D.2. ebfm_barwr_imm Procedure D.3. ebfm_barrd_wait Procedure D.4. ebfm_barrd_nowt Procedure D.5. ebfm_cfgwr_imm_wait Procedure D.6. ebfm_cfgwr_imm_nowt Procedure D.7. ebfm_cfgrd_wait Procedure D.8. ebfm_cfgrd_nowt Procedure D.9. BFM Configuration Procedures D.10. BFM Shared Memory Access Procedures D.11. BFM Log and Message Procedures D.12. Verilog HDL Formatting Functions
D.9. BFM Configuration Procedures x
D.9.1. ebfm_cfg_rp_ep Procedure D.9.2. ebfm_cfg_decode_bar Procedure
D.10. BFM Shared Memory Access Procedures x
D.10.1. Shared Memory Constants D.10.2. shmem_write Procedure D.10.3. shmem_read Function D.10.4. shmem_display Verilog HDL Function D.10.5. shmem_fill Procedure D.10.6. shmem_chk_ok Function
D.11. BFM Log and Message Procedures x
D.11.1. ebfm_display Verilog HDL Function D.11.2. ebfm_log_stop_sim Verilog HDL Function D.11.3. ebfm_log_set_suppressed_msg_mask Task D.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task D.11.5. ebfm_log_open Verilog HDL Function D.11.6. ebfm_log_close Verilog HDL Function
D.12. Verilog HDL Formatting Functions x
D.12.1. himage1 D.12.2. himage2 D.12.3. himage4 D.12.4. himage8 D.12.5. himage16 D.12.6. dimage1 D.12.7. dimage2 D.12.8. dimage3 D.12.9. dimage4 D.12.10. dimage5 D.12.11. dimage6 D.12.12. dimage7
1. Introduction
2. Quick Start Guide
3. Block and Interface Descriptions
4. Parameters
5. Designing with the IP Core
6. Registers
7. Design Example and Testbench
A. Troubleshooting and Observing the Link
B. Avalon-MM IP Variants Comparison
C. Root Port BFM
D. BFM Procedures and Functions
E. Root Port Enumeration
F. Document Revision History for Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

A.2.1.3.1. LTSSM Monitor Registers

You can program the LTSSM monitor registers to change the default behavior.

Table 68.  LTSSM Registers

Base Address

 LTSSM Address Access

Description

0x20000 5 0x00 RW

LTSSM Monitor Control register. The LTSSM Monitor Control includes the following fields:

  • [1:0]: Timer Resolution Control. Specifies the number of hip_reconfig_clk the PCIe* link remains in each LTSSM state. The following encodings are defined:
    • 2’b00: The main timer increments each hip_reconfig_clk cycle. This is the default value.
    • 2’b01: The main timer increments each 16 hip_reconfig_clk cycles.
    • 2’b10: The main timer increments each 256 hip_reconfig_clk cycles.

    • 2’b11: The main timer increments each <n> hip_reconfig_clk cycles. The Timer Resolution Step field defines <n>.

  • [17:2]: Timer Resolution Step. Specifies the value of <n> when Timer Resolution Control = 2'b11.
  • [18]: LTSSM FIFO reset. The following encodings are defined:
    • 1'b0: The LTSSM FIFO operates normally.
    • 1'b1: The LTSSM FIFO is in reset.
  • [19]: Reserved.
  • [20]: LTSSM State Match Enable. The following encodings are defined:
    • 1’b0: The LTSSM State match function is disabled
    • 1'b1: The LTSSM State match function is enabled.When the current LTSSM state matches a state stored in the LTSSM State Match register, the State Match Flag asserts.

  • [27:22] LTSSM State Match. When enabled, the LTSSM monitor compares the value in this register against each LTSSM state. If the values match, the LTSSM state match flag (offset address 0x01, bit 29) is set to 1.

  • [31:28]: Reserved.
0x01 RO

LTSSM Quick Debug Status register. The LTSSM Quick Debug Status register includes the following fields:

  • [9:0]: Number LTSSM States. Specifies the number of states currently stored in the FIFO.
  • [10]: LTSSM FIFO Full Flag. When asserted, the LTSSM FIFO is full.
  • [11]: LTSSM FIFO Empty Flag. When asserted, the LTSSM FIFO is empty.
  • [12]: Current PERSTN Status. Stores the current PERSTN value.
  • [13]: Current SERDES PLL Locked. The following encodings are defined:
    • 1'b0: The SERDES PLL is not locked.
    • 1'b1: The SERDES PLL is locked.
  • [14]: PCIe* Link Status. The following encodings are defined:
    • 1'b0: The link is down.
    • 1'b1: The link is up.
  • [16:15] Current PCIe* Data Rate. The following encodings are defined:
    • 2'b00: Reserved.
    • 2’b01=Gen1.
    • 2’b10=Gen2.
    • 2’b11=Gen3.
  • [17]: Native PHY Channel Locked to Data. The following encodings are defined:
    • 1'b0: At least one CDR channel is not locked to data.
    • 1'b1: All CDR channels are locked to data.
  • [21:18]: Current Number of PCIe* Active Lanes.
  • [22]: Reserved.
  • [28:23]: Current LTSSM State.
  • [29]: LTSSM State Match Flag. Asserts when the current state matches the state you specify in LTSSM State Match.
  • [31:30]: Reserved.
0x02 RO

LTSSM FIFO Output.

Reading this register is equivalent to reading one entry from the LTSSM FIFO. Reading this register also updates the LTSSM FIFO, 0x03. The following fields are defined:
  • [5:0] LTSSM State.

  • [7:6]: PCIe Current Speed.

  • [12:8:] PCIe Lane Act.

  • [13]: SerDes PLL Locked.

  • [14]: Link Up.

  • [15]: PERSTN.

  • [16]:Native PHY Channel 0. When asserted, the CDR is locked to data.

  • [17]: Native PHY Channel 1. When asserted, the CDR is locked to data.

  • [18]: Native PHY Channel 2. When asserted, the CDR is locked to data.

  • [19]: Native PHY Channel 3. When asserted, the CDR is locked to data.

  • [20]: Native PHY Channel 4. When asserted, the CDR is locked to data.
  • [21]: Native PHY Channel 5. When asserted, the CDR is locked to data.
  • [22]: Native PHY Channel 6. When asserted, the CDR is locked to data.
  • [23]: Native PHY Channel 7. When asserted, the CDR is locked to data.

  • [24]: Native PHY Channel 8. When asserted, the CDR is locked to data.

  • [25]: Native PHY Channel 9. When asserted, the CDR is locked to data.

  • [26]: Native PHY Channel 10. When asserted, the CDR is locked to data.

  • [27]: Native PHY Channel 11. When asserted, the CDR is locked to data.

  • [29]: Native PHY Channel 12. When asserted, the CDR is locked to data.

  • [28]: Native PHY Channel 13. When asserted, the CDR is locked to data.

  • [30]: Native PHY Channel 14. When asserted, the CDR is locked to data.

  • [31]: Native PHY Channel 15. When asserted, the CDR is locked to data.

0x03 RO

LTSSM FIFO Output [63:32]

[29:0] Main Timer. The timer resets to 0 on each LTSSM transition. The value in this register indicates how long the PCIe* link remains in each LTSSM state.

0x04 RW

LTSSM Skip State Storage Control register. Use this register to specify a maximum of 4 LTSSM states. When LTSSM State Skip Enable is on, the LTSSM FIFO does not store the specified state or states.

Refer to LTSSM State Encodings for the LTSSM Skip Field for the state encodings.

[5:0]: LTSSM State 1.

[6]: LTSSM State 1 Skip Enable.

[12:7]: LTSSM State 2.

[13]: LTSSM State 2 Skip Enable.

[19:14]: LTSSM State 3.

[20]: LTSSM State 3 Skip Enable.

[26:21]: LTSSM State 4.

[27]: LTSSM State 4 Skip Enable.

Table 69.  LTSSM State Encodings for the LTSSM Skip Field
State Encoding
Detect.Quiet 6'h00
Detect.Active 6'h01
Polling.Active 6'h02
Polling.Compliance 6'h03
Polling.Configuration 6'h04
PreDetect.Quiet 6'h05
Detect.Wait 6'h06
Configuration.Linkwidth.Start 6'h07
Configuration.Linkwidth.Accept 6'h08
Configuration.Lanenum.Wait 6'h09
Configuration.Lanenum.Accept 6'h0A
Configuration.Complete 6'h0B
Configuration.Idle 6'h0C
Recovery.RcvrLock 6'h0D
Recovery.Speed 6'h0E
Recovery.RcvrCfg 6'h0F
Recovery.Idle 6'h10
Recovery.Equalization Phase 0 6'h20
Recovery.Equalization Phase 1 6'h21
Recovery.Equalization Phase 2 6'h22
Recovery.Equalization Phase 3 6'h23
L0 6'h11
L0s 6'h12
L123.SendEIdle 6'h13
L1.Idle 6'h14
L2.Idle 6'h15
L2.TransmitWake 6'h16
Disabled.Entry 6'h17
Disabled.Idle 6'h18
Disabled 6'h19
Loopback.Entry 6'h1A
Loopback.Active 6'h1B
Loopback.Exit 6'h1C
Loopback.Exit.Timeout 6'h1D
HotReset.Entry 6'h1E
Hot.Reset 6'h1F
5 When the Enable PCIe Link Inspector AVMM Interface option is On, the base address of the LTSSM Registers becomes 0x8000. Use this value to access these registers via the pli_avmm_master_address[19:0] ports.
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