Cyclone® V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide

ID 683524
Date 6/02/2020
Public
Document Table of Contents

2.1.5. Understanding Physical Placement of the PCIe IP Core

For more information about physical placement of the PCIe blocks, refer to the links below. Contact your Intel sales representative for detailed information about channel and PLL usage.