Cyclone® V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide

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ID 683524
Date 6/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Cyclone V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Interrupts 7. Error Handling 8. IP Core Architecture 9. Transaction Layer Protocol (TLP) Details 10. Throughput Optimization 11. Design Implementation 12. Additional Features 13. Hard IP Reconfiguration 14. Transceiver PHY IP Reconfiguration 15. Testbench and Design Example 16. Debugging A. Frequently Asked Questions for PCI Express B. Lane Initialization and Reversal C. Document Revision History
1. Datasheet x
1.1. Cyclone V Avalon-ST Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Example Designs 1.7. Debug Features 1.8. IP Core Verification 1.9. Performance and Resource Utilization 1.10. Recommended Speed Grades 1.11. Creating a Design for PCI Express
1.8. IP Core Verification x
1.8.1. Compatibility Testing Environment
2. Getting Started with the Cyclone V Hard IP for PCI Express x
2.1. Qsys Design Flow 2.2. Modifying the Example Design 2.3. Using the IP Catalog To Generate Your Cyclone V Hard IP for PCI Express as a Separate Component
2.1. Qsys Design Flow x
2.1.1. Generating the Testbench 2.1.2. Simulating the Example Design 2.1.3. Generating Synthesis Files 2.1.4. Understanding the Files Generated 2.1.5. Understanding Physical Placement of the PCIe IP Core 2.1.6. Compiling the Design in the Quartus® Prime Software
3. Parameter Settings x
3.1. Avalon-ST System Settings 3.2. Link Capabilities 3.3. Port Function Parameters Shared Across All Port Functions 3.4. Port Function Parameters Defined Separately for All Port Functions
3.3. Port Function Parameters Shared Across All Port Functions x
3.3.1. Device Capabilities 3.3.2. Error Reporting 3.3.3. Link Capabilities 3.3.4. Slot Capabilities 3.3.5. Power Management
3.4. Port Function Parameters Defined Separately for All Port Functions x
3.4.1. Base Address Register (BAR) and Expansion ROM Settings 3.4.2. Base and Limit Registers for Root Ports 3.4.3. Device Identification Registers for Function <n> 3.4.4. Func <n> Device 3.4.5. Func <n> Link 3.4.6. Func <n> MSI and MSI-X Capabilities 3.4.7. Func <n> Legacy Interrupt
4. Interfaces and Signal Descriptions x
4.1. Clock Signals 4.2. Reset, Status, and Link Training Signals 4.3. ECRC Forwarding 4.4. Error Signals 4.5. Interrupts for Endpoints 4.6. Interrupts for Root Ports 4.7. Completion Side Band Signals 4.8. LMI Signals 4.9. Transaction Layer Configuration Space Signals 4.10. Hard IP Reconfiguration Interface 4.11. Power Management Signals 4.12. Physical Layer Interface Signals
4.9. Transaction Layer Configuration Space Signals x
4.9.1. Configuration Space Register Access Timing 4.9.2. Configuration Space Register Access
4.12. Physical Layer Interface Signals x
4.12.1. Serial Data Signals 4.12.2. PIPE Interface Signals 4.12.3. Test Signals
4.12.1. Serial Data Signals x
4.12.1.1. Physical Layout of Hard IP in Cyclone V Devices 4.12.1.2. Channel Placement in Cyclone V Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. Advanced Error Reporting Capability
5.5. Intel-Defined VSEC Registers x
5.5.1. CvP Registers
5.6. Advanced Error Reporting Capability x
5.6.1. Uncorrectable Internal Error Mask Register 5.6.2. Uncorrectable Internal Error Status Register 5.6.3. Correctable Internal Error Mask Register 5.6.4. Correctable Internal Error Status Register
6. Interrupts x
6.1. Interrupts for Endpoints 6.2. Interrupts for Root Ports
6.1. Interrupts for Endpoints x
6.1.1. MSI and Legacy Interrupts 6.1.2. MSI-X 6.1.3. Implementing MSI-X Interrupts 6.1.4. Legacy Interrupts
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
8. IP Core Architecture x
8.1. Top-Level Interfaces 8.2. Transaction Layer 8.3. Data Link Layer 8.4. Physical Layer 8.5. Multi-Function Support
8.1. Top-Level Interfaces x
8.1.1. Avalon-ST Interface 8.1.2. Clocks and Reset 8.1.3. Local Management Interface (LMI Interface) 8.1.4. Hard IP Reconfiguration 8.1.5. Transceiver Reconfiguration 8.1.6. Interrupts 8.1.7. PIPE
8.2. Transaction Layer x
8.2.1. Configuration Space
9. Transaction Layer Protocol (TLP) Details x
9.1. Supported Message Types 9.2. Transaction Layer Routing Rules 9.3. Receive Buffer Reordering
9.1. Supported Message Types x
9.1.1. INTX Messages 9.1.2. Power Management Messages 9.1.3. Error Signaling Messages 9.1.4. Locked Transaction Message 9.1.5. Slot Power Limit Message 9.1.6. Vendor-Defined Messages 9.1.7. Hot Plug Messages
9.3. Receive Buffer Reordering x
9.3.1. Using Relaxed Ordering
10. Throughput Optimization x
10.1. Throughput of Posted Writes 10.2. Throughput of Non-Posted Reads
11. Design Implementation x
11.1. Making Analog QSF Assignments Using the Assignment Editor 11.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 11.3. Recommended Reset Sequence to Avoid Link Training Issues 11.4. SDC Timing Constraints
12. Additional Features x
12.1. Configuration over Protocol (CvP) 12.2. Autonomous Mode 12.3. ECRC
12.2. Autonomous Mode x
12.2.1. Enabling Autonomous Mode 12.2.2. Enabling CvP Initialization
12.3. ECRC x
12.3.1. ECRC on the RX Path 12.3.2. ECRC on the TX Path
14. Transceiver PHY IP Reconfiguration x
14.1. Connecting the Transceiver Reconfiguration Controller IP Core 14.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
15. Testbench and Design Example x
15.1. Endpoint Testbench 15.2. Root Port Testbench 15.3. Test Driver Module 15.4. Root Port Design Example 15.5. Root Port BFM Overview 15.6. BFM Procedures and Functions 15.7. Setting Up Simulation
15.1. Endpoint Testbench x
15.1.1. Endpoint Testbench for SR-IOV
15.5. Root Port BFM Overview x
15.5.1. BFM Memory Map 15.5.2. Configuration Space Bus and Device Numbering 15.5.3. Configuration of Root Port and Endpoint 15.5.4. Issuing Read and Write Transactions to the Application Layer
15.6. BFM Procedures and Functions x
15.6.1. ebfm_barwr Procedure 15.6.2. ebfm_barwr_imm Procedure 15.6.3. ebfm_barrd_wait Procedure 15.6.4. ebfm_barrd_nowt Procedure 15.6.5. ebfm_cfgwr_imm_wait Procedure 15.6.6. ebfm_cfgwr_imm_nowt Procedure 15.6.7. ebfm_cfgrd_wait Procedure 15.6.8. ebfm_cfgrd_nowt Procedure 15.6.9. BFM Configuration Procedures 15.6.10. BFM Shared Memory Access Procedures 15.6.11. BFM Log and Message Procedures 15.6.12. Verilog HDL Formatting Functions
15.6.9. BFM Configuration Procedures x
15.6.9.1. ebfm_cfg_rp_ep Procedure 15.6.9.2. ebfm_cfg_decode_bar Procedure
15.6.10. BFM Shared Memory Access Procedures x
15.6.10.1. Shared Memory Constants 15.6.10.2. shmem_write Task 15.6.10.3. shmem_read Function 15.6.10.4. shmem_display Verilog HDL Function 15.6.10.5. shmem_fill Procedure 15.6.10.6. shmem_chk_ok Function
15.6.11. BFM Log and Message Procedures x
15.6.11.1. ebfm_display Verilog HDL Function 15.6.11.2. ebfm_log_stop_sim Verilog HDL Function 15.6.11.3. ebfm_log_set_suppressed_msg_mask Task 15.6.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 15.6.11.5. ebfm_log_open Verilog HDL Function 15.6.11.6. ebfm_log_close Verilog HDL Function
15.6.12. Verilog HDL Formatting Functions x
15.6.12.1. himage1 15.6.12.2. himage2 15.6.12.3. himage4 15.6.12.4. himage8 15.6.12.5. himage16 15.6.12.6. dimage1 15.6.12.7. dimage2 15.6.12.8. dimage3 15.6.12.9. dimage4 15.6.12.10. dimage5 15.6.12.11. dimage6 15.6.12.12. dimage7
15.7. Setting Up Simulation x
15.7.1. Changing Between Serial and PIPE Simulation 15.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants 15.7.3. Viewing the Important PIPE Interface Signals 15.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 15.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations 15.7.6. Changing between the Hard and Soft Reset Controller
16. Debugging x
16.1. Hardware Bring-Up Issues 16.2. Link Training 16.3. Use Third-Party PCIe Analyzer 16.4. BIOS Enumeration Issues
16.2. Link Training x
16.2.1. Link Hangs in L0 State
C. Document Revision History x
C.1. Document Revision History of the Cyclone V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Cyclone V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts
7. Error Handling
8. IP Core Architecture
9. Transaction Layer Protocol (TLP) Details
10. Throughput Optimization
11. Design Implementation
12. Additional Features
13. Hard IP Reconfiguration
14. Transceiver PHY IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Frequently Asked Questions for PCI Express
B. Lane Initialization and Reversal
C. Document Revision History

4.9. Transaction Layer Configuration Space Signals

Table 31.  Configuration Space Signals

Signal

Direction

Description

tl_cfg_add[6:0]

0utput

Address of the register that has been updated. This signal is an index indicating which Configuration Space register information is being driven onto tl_cfg_ctl. The indexing is defined in Multiplexed Configuration Register Information Available on tl_cfg_ctl . The index increments every 8coreclkout cycle. The index increments every 8 coreclkout cycles. The index consists of the following 2 fields:

  • [6:4] - indicates the function number whose information is being presented on tl_cfg_ctl
  • [3:0] - the tl_cfg_ctl tl_cfg_ctl multiplexor index
tl_cfg_ctl[31:0]

0utput

The signal is multiplexed and contains the contents of the Configuration Space registers. The indexing is defined in Multiplexed Configuration Register Information Available on tl_cfg_ctl .

tl_cfg_ctl_wr

0utput

Write signal. This signal toggles when tl_cfg_ctl has been updated (every 8 coreclkout cycles). The toggle edge marks where the tl_cfg_ctl data changes. You can use this edge as a reference to determine when the data is safe to sample.
tl_cfg_sts[122:0]

0utput

Configuration status bits. This information updates every coreclkout cycle. Bits[52:0] record status information for function0. Bits[62:53] record information for function1. Bits[72:63] record information for function 2, and so on. Refer to the following table for a detailed description of the status bits.
tl_cfg_sts_wr

0utput

Write signal. This signal toggles when tl_cfg_stshas been updated (every 8 core_clk cycles). The toggle marks the edge where tl_cfg_sts data changes. You can use this edge as a reference to determine when the data is safe to sample.
hpg_ctrler[4:0]

Input

The hpg_ctrler signals are only available in Root Port mode and when the Slot capability register is enabled. Refer to the Slot register and Slot capability register parameters in Table 6–9 on page 6–10. For Endpoint variations the hpg_ctrler input should be hardwired to 0s. The bits have the following meanings:

Input

  • [0]: Attention button pressed. This signal should be asserted when the attention button is pressed. If no attention button exists for the slot, this bit should be hardwired to 0, and the Attention Button Present bit (bit[0]) in the Slot capability register parameter is set to 0.

Input

  • [1]: Presence detect. This signal should be asserted when a presence detect circuit detects a presence detect change in the slot.

Input

  • [2]: Manually-operated retention latch (MRL) sensor changed. This signal should be asserted when an MRL sensor indicates that the MRL is Open. If an MRL Sensor does not exist for the slot, this bit should be hardwired to 0, and the MRL Sensor Present bit (bit[2]) in the Slot capability register parameter is set to 0.

Input

  • [3]: Power fault detected. This signal should be asserted when the power controller detects a power fault for this slot. If this slot has no power controller, this bit should be hardwired to 0, and the Power Controller Present bit (bit[1]) in the Slot capability register parameter is set to 0.

Input

  • [4]: Power controller status. This signal is used to set the command completed bit of the Slot Status register. Power controller status is equal to the power controller control signal. If this slot has no power controller, this bit should be hardwired to 0 and the Power Controller Present bit (bit[1]) in the Slot capability register is set to 0.
Table 32.  Mapping Between tl_cfg_sts and Configuration Space Registers

tl_cfg_sts

Configuration Space Register

Description

[62:59] Func1

[72:69] Func2

[82:79] Func3

[92:89] Func4

[102:99] Func5

[112:109] Func6

[122:119] Func7

Device Status Reg[3:0]

Records the following errors:

  • Bit 3: unsupported request
  • Bit 2: fatal error
  • Bit 1: non-fatal error
  • Bit 0: correctable error

[58:54] Func1

[68:64] Func2

[78:74] Func3

[88:84] Func4

[98:94] Func5

[108:104] Func6

[118:114] Func7

Link Status Reg[15:11]

Link status bits as follows:

  • Bit 15: link autonomous bandwidth status
  • Bit 14: link bandwidth management status
  • Bit 13: Data Link Layer link active - This bit is only active for Root Ports. It is 0 for Endpoints.
  • Bit 12: slot clock configuration
  • Bit 11: link training

[53] Func1

[63] Func2

[73] Func3

[83] Func4

[93] Func5

[103] Func6

[113] Func7

Secondary Status Reg[8]

6th primary command status error bit. Master data parity error.

[52:49]

Device Status Reg[3:0]

Records the following errors:

  • Bit 3: unsupported request detected
  • Bit 2: fatal error detected
  • Bit 1: non‑fatal error detected
  • Bit 0: correctable error detected

[48]

Slot Status Register[8]

Data Link Layer state changed

[47]

Slot Status Reg[4]

Command completed. (The hot plug controller completed a command.)

[46:31]

Link Status Reg[15:0]

Records the following link status information:

  • Bit 15: link autonomous bandwidth status
  • Bit 14: link bandwidth management status
  • Bit 13: Data Link Layer link active - This bit is only active for Root Ports. It is 0 for Endpoints.
  • Bit 12: Slot clock configuration
  • Bit 11: Link Training
  • Bit 10: Undefined
  • Bits[9:4]: Negotiated Link Width
  • Bits[3:0] Link Speed

[30]

Link Status 2 Reg[0]

Current de-emphasis level.

[29:25]

Status Reg[15:11]

Records the following 5 primary command status errors:

  • Bit 15: detected parity error
  • Bit 14: signaled system error
  • Bit 13: received master abort
  • Bit 12: received target abort
  • Bit 11: signaled target abort

[24]

Secondary Status Reg[8]

Master data parity error

[23:6]

Root Status Reg[17:0]

Records the following PME status information:

  • Bit 17: PME pending
  • Bit 16: PME status
  • Bits[15:0]: PME request ID[15:0]

[5:1]

Secondary Status Reg[15:11]

Records the following 5 secondary command status errors:

  • Bit 15: detected parity error
  • Bit 14: received system error
  • Bit 13: received master abort
  • Bit 12: received target abort
  • Bit 11: signaled target abort

[0]

Secondary Status Reg[8]

Master Data Parity Error


Section Content
Configuration Space Register Access Timing
Configuration Space Register Access

Level Two Title