Cyclone® V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide

ID 683524
Date 6/02/2020
Public
Document Table of Contents

4.6. Interrupts for Root Ports

Table 28.  Interrupt Signals for Root Ports

Signal

Direction

Description

int_status[3:0]

Output

These signals drive legacy interrupts to the Application Layer as follows:

  • int_status[0]: interrupt signal A
  • int_status[1]: interrupt signal B
  • int_status[2]: interrupt signal C
  • int_status[3]: interrupt signal D
aer_msi_num[4:0] Input Advanced error reporting (AER) MSI number. Provides the low-order message data bits to be sent in the message data field of the MSI messages associated with the AER capability structure. Only bits that are enabled by the MSI Message Control register are used. For Root Ports only.
pex_msi_num[4:0] Input Power management MSI number. This signal provides the low-order message data bits to be sent in the message data field of MSI messages associated with the PCI Express capability structure. Only bits that are enabled by the MSI Message Control register are used. For Root Ports only.
serr_out

Output

System Error: This signal only applies to Root Port designs that report each system error detected, assuming the proper enabling bits are asserted in the Root Control and Device Control registers. If enabled, serr_out is asserted for a single clock cycle when a system error occurs. System errors are described in the PCI Express Base Specification 2.1 or 3.0 in the Root Control register.