Cyclone® V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide

ID 683524
Date 6/02/2020
Public
Document Table of Contents

4.5. Interrupts for Endpoints

Refer to Interrupts for detailed information about all interrupt mechanisms.

Table 27.  Interrupt Signals for Endpoints

Signal

Direction

Description

app_msi_req

Input

Application Layer MSI request. Assertion causes an MSI posted write TLP to be generated based on the MSI configuration register values and the app_msi_tc and app_msi_num input ports.

app_msi_ack

Output

Application Layer MSI acknowledge. This signal acknowledges the Application Layer's request for an MSI interrupt.

app_msi_tc[2:0]

Input

Application Layer MSI traffic class. This signal indicates the traffic class used to send the MSI (unlike INTX interrupts, any traffic class can be used to send MSIs).

app_msi_num[4:0]

Input

MSI number of the Application Layer. This signal provides the low order message data bits to be sent in the message data field of MSI messages requested by app_msi_req. Only bits that are enabled by the MSI Message Control register apply.

app_int_sts_vec[7:0]

Input

Controls legacy interrupt generation. The Interrupt Handler Module in the Application Layer asserts app_int_sts_vec[<n>]. In response, the PCI Express* Endpoint generates an Assert_INTx message TLP which it sends upstream. After the app_msi_ack signal is asserted, the Interrupt Handler Module deasserts app_int_sts_vec[<n>]. In response, the Endpoint sends a Deassert_INTx message TLP upstream.