Cyclone® V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide

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ID 683524
Date 6/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Cyclone V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Interrupts 7. Error Handling 8. IP Core Architecture 9. Transaction Layer Protocol (TLP) Details 10. Throughput Optimization 11. Design Implementation 12. Additional Features 13. Hard IP Reconfiguration 14. Transceiver PHY IP Reconfiguration 15. Testbench and Design Example 16. Debugging A. Frequently Asked Questions for PCI Express B. Lane Initialization and Reversal C. Document Revision History
1. Datasheet x
1.1. Cyclone V Avalon-ST Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Example Designs 1.7. Debug Features 1.8. IP Core Verification 1.9. Performance and Resource Utilization 1.10. Recommended Speed Grades 1.11. Creating a Design for PCI Express
1.8. IP Core Verification x
1.8.1. Compatibility Testing Environment
2. Getting Started with the Cyclone V Hard IP for PCI Express x
2.1. Qsys Design Flow 2.2. Modifying the Example Design 2.3. Using the IP Catalog To Generate Your Cyclone V Hard IP for PCI Express as a Separate Component
2.1. Qsys Design Flow x
2.1.1. Generating the Testbench 2.1.2. Simulating the Example Design 2.1.3. Generating Synthesis Files 2.1.4. Understanding the Files Generated 2.1.5. Understanding Physical Placement of the PCIe IP Core 2.1.6. Compiling the Design in the Quartus® Prime Software
3. Parameter Settings x
3.1. Avalon-ST System Settings 3.2. Link Capabilities 3.3. Port Function Parameters Shared Across All Port Functions 3.4. Port Function Parameters Defined Separately for All Port Functions
3.3. Port Function Parameters Shared Across All Port Functions x
3.3.1. Device Capabilities 3.3.2. Error Reporting 3.3.3. Link Capabilities 3.3.4. Slot Capabilities 3.3.5. Power Management
3.4. Port Function Parameters Defined Separately for All Port Functions x
3.4.1. Base Address Register (BAR) and Expansion ROM Settings 3.4.2. Base and Limit Registers for Root Ports 3.4.3. Device Identification Registers for Function <n> 3.4.4. Func <n> Device 3.4.5. Func <n> Link 3.4.6. Func <n> MSI and MSI-X Capabilities 3.4.7. Func <n> Legacy Interrupt
4. Interfaces and Signal Descriptions x
4.1. Clock Signals 4.2. Reset, Status, and Link Training Signals 4.3. ECRC Forwarding 4.4. Error Signals 4.5. Interrupts for Endpoints 4.6. Interrupts for Root Ports 4.7. Completion Side Band Signals 4.8. LMI Signals 4.9. Transaction Layer Configuration Space Signals 4.10. Hard IP Reconfiguration Interface 4.11. Power Management Signals 4.12. Physical Layer Interface Signals
4.9. Transaction Layer Configuration Space Signals x
4.9.1. Configuration Space Register Access Timing 4.9.2. Configuration Space Register Access
4.12. Physical Layer Interface Signals x
4.12.1. Serial Data Signals 4.12.2. PIPE Interface Signals 4.12.3. Test Signals
4.12.1. Serial Data Signals x
4.12.1.1. Physical Layout of Hard IP in Cyclone V Devices 4.12.1.2. Channel Placement in Cyclone V Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. Advanced Error Reporting Capability
5.5. Intel-Defined VSEC Registers x
5.5.1. CvP Registers
5.6. Advanced Error Reporting Capability x
5.6.1. Uncorrectable Internal Error Mask Register 5.6.2. Uncorrectable Internal Error Status Register 5.6.3. Correctable Internal Error Mask Register 5.6.4. Correctable Internal Error Status Register
6. Interrupts x
6.1. Interrupts for Endpoints 6.2. Interrupts for Root Ports
6.1. Interrupts for Endpoints x
6.1.1. MSI and Legacy Interrupts 6.1.2. MSI-X 6.1.3. Implementing MSI-X Interrupts 6.1.4. Legacy Interrupts
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
8. IP Core Architecture x
8.1. Top-Level Interfaces 8.2. Transaction Layer 8.3. Data Link Layer 8.4. Physical Layer 8.5. Multi-Function Support
8.1. Top-Level Interfaces x
8.1.1. Avalon-ST Interface 8.1.2. Clocks and Reset 8.1.3. Local Management Interface (LMI Interface) 8.1.4. Hard IP Reconfiguration 8.1.5. Transceiver Reconfiguration 8.1.6. Interrupts 8.1.7. PIPE
8.2. Transaction Layer x
8.2.1. Configuration Space
9. Transaction Layer Protocol (TLP) Details x
9.1. Supported Message Types 9.2. Transaction Layer Routing Rules 9.3. Receive Buffer Reordering
9.1. Supported Message Types x
9.1.1. INTX Messages 9.1.2. Power Management Messages 9.1.3. Error Signaling Messages 9.1.4. Locked Transaction Message 9.1.5. Slot Power Limit Message 9.1.6. Vendor-Defined Messages 9.1.7. Hot Plug Messages
9.3. Receive Buffer Reordering x
9.3.1. Using Relaxed Ordering
10. Throughput Optimization x
10.1. Throughput of Posted Writes 10.2. Throughput of Non-Posted Reads
11. Design Implementation x
11.1. Making Analog QSF Assignments Using the Assignment Editor 11.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 11.3. Recommended Reset Sequence to Avoid Link Training Issues 11.4. SDC Timing Constraints
12. Additional Features x
12.1. Configuration over Protocol (CvP) 12.2. Autonomous Mode 12.3. ECRC
12.2. Autonomous Mode x
12.2.1. Enabling Autonomous Mode 12.2.2. Enabling CvP Initialization
12.3. ECRC x
12.3.1. ECRC on the RX Path 12.3.2. ECRC on the TX Path
14. Transceiver PHY IP Reconfiguration x
14.1. Connecting the Transceiver Reconfiguration Controller IP Core 14.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
15. Testbench and Design Example x
15.1. Endpoint Testbench 15.2. Root Port Testbench 15.3. Test Driver Module 15.4. Root Port Design Example 15.5. Root Port BFM Overview 15.6. BFM Procedures and Functions 15.7. Setting Up Simulation
15.1. Endpoint Testbench x
15.1.1. Endpoint Testbench for SR-IOV
15.5. Root Port BFM Overview x
15.5.1. BFM Memory Map 15.5.2. Configuration Space Bus and Device Numbering 15.5.3. Configuration of Root Port and Endpoint 15.5.4. Issuing Read and Write Transactions to the Application Layer
15.6. BFM Procedures and Functions x
15.6.1. ebfm_barwr Procedure 15.6.2. ebfm_barwr_imm Procedure 15.6.3. ebfm_barrd_wait Procedure 15.6.4. ebfm_barrd_nowt Procedure 15.6.5. ebfm_cfgwr_imm_wait Procedure 15.6.6. ebfm_cfgwr_imm_nowt Procedure 15.6.7. ebfm_cfgrd_wait Procedure 15.6.8. ebfm_cfgrd_nowt Procedure 15.6.9. BFM Configuration Procedures 15.6.10. BFM Shared Memory Access Procedures 15.6.11. BFM Log and Message Procedures 15.6.12. Verilog HDL Formatting Functions
15.6.9. BFM Configuration Procedures x
15.6.9.1. ebfm_cfg_rp_ep Procedure 15.6.9.2. ebfm_cfg_decode_bar Procedure
15.6.10. BFM Shared Memory Access Procedures x
15.6.10.1. Shared Memory Constants 15.6.10.2. shmem_write Task 15.6.10.3. shmem_read Function 15.6.10.4. shmem_display Verilog HDL Function 15.6.10.5. shmem_fill Procedure 15.6.10.6. shmem_chk_ok Function
15.6.11. BFM Log and Message Procedures x
15.6.11.1. ebfm_display Verilog HDL Function 15.6.11.2. ebfm_log_stop_sim Verilog HDL Function 15.6.11.3. ebfm_log_set_suppressed_msg_mask Task 15.6.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 15.6.11.5. ebfm_log_open Verilog HDL Function 15.6.11.6. ebfm_log_close Verilog HDL Function
15.6.12. Verilog HDL Formatting Functions x
15.6.12.1. himage1 15.6.12.2. himage2 15.6.12.3. himage4 15.6.12.4. himage8 15.6.12.5. himage16 15.6.12.6. dimage1 15.6.12.7. dimage2 15.6.12.8. dimage3 15.6.12.9. dimage4 15.6.12.10. dimage5 15.6.12.11. dimage6 15.6.12.12. dimage7
15.7. Setting Up Simulation x
15.7.1. Changing Between Serial and PIPE Simulation 15.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants 15.7.3. Viewing the Important PIPE Interface Signals 15.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 15.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations 15.7.6. Changing between the Hard and Soft Reset Controller
16. Debugging x
16.1. Hardware Bring-Up Issues 16.2. Link Training 16.3. Use Third-Party PCIe Analyzer 16.4. BIOS Enumeration Issues
16.2. Link Training x
16.2.1. Link Hangs in L0 State
C. Document Revision History x
C.1. Document Revision History of the Cyclone V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Cyclone V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts
7. Error Handling
8. IP Core Architecture
9. Transaction Layer Protocol (TLP) Details
10. Throughput Optimization
11. Design Implementation
12. Additional Features
13. Hard IP Reconfiguration
14. Transceiver PHY IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Frequently Asked Questions for PCI Express
B. Lane Initialization and Reversal
C. Document Revision History

4.12.2. PIPE Interface Signals

These PIPE signals are available for Gen1, Gen2, and Gen3 variants so that you can simulate using either the serial or the PIPE interface. Simulation is much faster using the PIPE interface because the PIPE simulation bypasses the SERDES model . By default, the PIPE interface data width is 8 bits for Gen1 and Gen2 and 32 bits for Gen3. You can use the PIPE interface for simulation even though your actual design includes a serial interface to the internal transceivers. However, it is not possible to use the Hard IP PIPE interface in hardware, including probing these signals using Signal Tap.

Intel® Cyclone® 10 GX devices do not support the Gen3 data rate.

Table 39.  PIPE Interface Signals

Signal

Direction

Description

txdata0[7:0]

Output

Transmit data <n>. This bus transmits data on lane <n>.

txdatak0

Output

Transmit data control <n>. This signal serves as the control bit for txdata <n>.

txcompl0

Output

Transmit compliance <n>. This signal forces the running disparity to negative in Compliance Mode (negative COM character).

txdataskip0

Output

For Gen3 operation. Allows the MAC to instruct the TX interface to ignore the TX data interface for one clock cycle. The following encodings are defined:

  • 1’b0: TX data is invalid
  • 1’b1: TX data is valid
txdeemph0

Output

Transmit de-emphasis selection. The Intel® Arria® 10 Hard IP for PCI Express sets the value for this signal based on the indication received from the other end of the link during the Training Sequences (TS). You do not need to change this value.

txdetectrx0

Output

Transmit detect receive <n>. This signal tells the PHY layer to start a receive detection operation or to begin loopback.

txelecidle0

Output

Transmit electrical idle <n>. This signal forces the TX output to electrical idle.

txswing

Output

When asserted, indicates full swing for the transmitter voltage. When deasserted indicates half swing.

txmargin[2:0]

Output

Transmit VOD margin selection. The value for this signal is based on the value from the Link Control 2 Register. Available for simulation only.

rxdata0[7:0]

Input

Receive data <n>. This bus receives data on lane <n>.

rxdatak0

Input

Receive data control <n>. This signal serves as the control bit for rxdata <n>. Bit 0 corresponds to the lowest-order byte of rxdata, and so on. A value of 0 indicates a data byte. A value of 1 indicates a control byte. For Gen1 and Gen2 only.

rxelecidle0

Input

Receive electrical idle <n>. When asserted, indicates detection of an electrical idle.

rxpolarity0

Output

Receive polarity <n>. This signal instructs the PHY layer to invert the polarity of the 8B/10B receiver decoding block.

rxstatus0[2:0]

Input

Receive status <n>. This signal encodes receive status, including error codes for the receive data stream and receiver detection.

rxvalid0

Input

Receive valid <n>. This signal indicates symbol lock and valid data on rxdata <n> and rxdatak <n>.

phystatus0

Input

PHY status <n>. This signal communicates completion of several PHY requests.

powerdown0[1:0]

Output

Power down <n>. This signal requests the PHY to change its power state to the specified state (P0, P0s, P1, or P2).

simu_mode_pipe

Input

When set to 1, the PIPE interface is in simulation mode.

sim_pipe_rate[1:0]

Output

The 2‑bit encodings have the following meanings:

  • 2’b00: Gen1 rate (2.5 Gbps)
  • 2’b01: Gen2 rate (5.0 Gbps)
  • 2’b10: Gen3 rate (8.0 Gbps)
sim_pipe_pclk_in

Input

This clock is used for PIPE simulation only, and is derived from the refclk. It is the PIPE interface clock used for PIPE mode simulation.

sim_pipe_pclk_out

Output

TX datapath clock to the BFM PHY. pclk_out is derived from refclk and provides the source synchronous clock for TX data from the PHY.

sim_pipe_clk250_out

Output

Used to generate pclk.

sim_pipe_clk500_out

Output

Used to generate pclk.

sim_pipe_ltssmstate0[4:0]

Input and Output

LTSSM state: The LTSSM state machine encoding defines the following states:

  • 5’b00000: Detect.Quiet
  • 5’b00001: Detect.Active
  • 5’b00010: Polling.Active
  • 5’b 00011: Polling.Compliance
  • 5’b 00100: Polling.Configuration
  • 5’b00101: Polling.Speed
  • 5’b00110: config.LinkwidthsStart
  • 5’b 00111: Config.Linkaccept
  • 5’b 01000: Config.Lanenumaccept
  • 5’b01001: Config.Lanenumwait
  • 5’b01010: Config.Complete
  • 5’b 01011: Config.Idle
  • 5’b01100: Recovery.Rcvlock
  • 5’b01101: Recovery.Rcvconfig
  • 5’b01110: Recovery.Idle
  • 5’b 01111: L0
  • 5’b10000: Disable
  • 5’b10001: Loopback.Entry
  • 5’b10010: Loopback.Active
  • 5’b10011: Loopback.Exit
  • 5’b10100: Hot.Reset
  • 5’b10101: L0s
  • 5’b11001: L2.transmit.Wake
  • 5’b11010: Recovery.Speed
  • 5’b11011: Recovery.Equalization, Phase 0
  • 5’b11100: Recovery.Equalization, Phase 1
  • 5’b11101: Recovery.Equalization, Phase 2
  • 5’b11110: Recovery.Equalization, Phase 3
  • 5’b11111: Recovery.Equalization, Done
rxfreqlocked0

Input

When asserted indicates that the pclk_in used for PIPE simulation is valid.

eidleinfersel0[2:0]

Output

Electrical idle entry inference mechanism selection. The following encodings are defined:

  • 3'b0xx: Electrical Idle Inference not required in current LTSSM state
  • 3'b100: Absence of COM/SKP Ordered Set in the 128 us window for Gen1 or Gen2
  • 3'b101: Absence of TS1/TS2 Ordered Set in a 1280 UI interval for Gen1 or Gen2
  • 3'b110: Absence of Electrical Idle Exit in 2000 UI interval for Gen1 and 16000 UI interval for Gen2
  • 3'b111: Absence of Electrical idle exit in 128 us window for Gen1
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