Cyclone® V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide

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ID 683524
Date 6/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Cyclone V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Interrupts 7. Error Handling 8. IP Core Architecture 9. Transaction Layer Protocol (TLP) Details 10. Throughput Optimization 11. Design Implementation 12. Additional Features 13. Hard IP Reconfiguration 14. Transceiver PHY IP Reconfiguration 15. Testbench and Design Example 16. Debugging A. Frequently Asked Questions for PCI Express B. Lane Initialization and Reversal C. Document Revision History
1. Datasheet x
1.1. Cyclone V Avalon-ST Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Example Designs 1.7. Debug Features 1.8. IP Core Verification 1.9. Performance and Resource Utilization 1.10. Recommended Speed Grades 1.11. Creating a Design for PCI Express
1.8. IP Core Verification x
1.8.1. Compatibility Testing Environment
2. Getting Started with the Cyclone V Hard IP for PCI Express x
2.1. Qsys Design Flow 2.2. Modifying the Example Design 2.3. Using the IP Catalog To Generate Your Cyclone V Hard IP for PCI Express as a Separate Component
2.1. Qsys Design Flow x
2.1.1. Generating the Testbench 2.1.2. Simulating the Example Design 2.1.3. Generating Synthesis Files 2.1.4. Understanding the Files Generated 2.1.5. Understanding Physical Placement of the PCIe IP Core 2.1.6. Compiling the Design in the Quartus® Prime Software
3. Parameter Settings x
3.1. Avalon-ST System Settings 3.2. Link Capabilities 3.3. Port Function Parameters Shared Across All Port Functions 3.4. Port Function Parameters Defined Separately for All Port Functions
3.3. Port Function Parameters Shared Across All Port Functions x
3.3.1. Device Capabilities 3.3.2. Error Reporting 3.3.3. Link Capabilities 3.3.4. Slot Capabilities 3.3.5. Power Management
3.4. Port Function Parameters Defined Separately for All Port Functions x
3.4.1. Base Address Register (BAR) and Expansion ROM Settings 3.4.2. Base and Limit Registers for Root Ports 3.4.3. Device Identification Registers for Function <n> 3.4.4. Func <n> Device 3.4.5. Func <n> Link 3.4.6. Func <n> MSI and MSI-X Capabilities 3.4.7. Func <n> Legacy Interrupt
4. Interfaces and Signal Descriptions x
4.1. Clock Signals 4.2. Reset, Status, and Link Training Signals 4.3. ECRC Forwarding 4.4. Error Signals 4.5. Interrupts for Endpoints 4.6. Interrupts for Root Ports 4.7. Completion Side Band Signals 4.8. LMI Signals 4.9. Transaction Layer Configuration Space Signals 4.10. Hard IP Reconfiguration Interface 4.11. Power Management Signals 4.12. Physical Layer Interface Signals
4.9. Transaction Layer Configuration Space Signals x
4.9.1. Configuration Space Register Access Timing 4.9.2. Configuration Space Register Access
4.12. Physical Layer Interface Signals x
4.12.1. Serial Data Signals 4.12.2. PIPE Interface Signals 4.12.3. Test Signals
4.12.1. Serial Data Signals x
4.12.1.1. Physical Layout of Hard IP in Cyclone V Devices 4.12.1.2. Channel Placement in Cyclone V Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. Advanced Error Reporting Capability
5.5. Intel-Defined VSEC Registers x
5.5.1. CvP Registers
5.6. Advanced Error Reporting Capability x
5.6.1. Uncorrectable Internal Error Mask Register 5.6.2. Uncorrectable Internal Error Status Register 5.6.3. Correctable Internal Error Mask Register 5.6.4. Correctable Internal Error Status Register
6. Interrupts x
6.1. Interrupts for Endpoints 6.2. Interrupts for Root Ports
6.1. Interrupts for Endpoints x
6.1.1. MSI and Legacy Interrupts 6.1.2. MSI-X 6.1.3. Implementing MSI-X Interrupts 6.1.4. Legacy Interrupts
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
8. IP Core Architecture x
8.1. Top-Level Interfaces 8.2. Transaction Layer 8.3. Data Link Layer 8.4. Physical Layer 8.5. Multi-Function Support
8.1. Top-Level Interfaces x
8.1.1. Avalon-ST Interface 8.1.2. Clocks and Reset 8.1.3. Local Management Interface (LMI Interface) 8.1.4. Hard IP Reconfiguration 8.1.5. Transceiver Reconfiguration 8.1.6. Interrupts 8.1.7. PIPE
8.2. Transaction Layer x
8.2.1. Configuration Space
9. Transaction Layer Protocol (TLP) Details x
9.1. Supported Message Types 9.2. Transaction Layer Routing Rules 9.3. Receive Buffer Reordering
9.1. Supported Message Types x
9.1.1. INTX Messages 9.1.2. Power Management Messages 9.1.3. Error Signaling Messages 9.1.4. Locked Transaction Message 9.1.5. Slot Power Limit Message 9.1.6. Vendor-Defined Messages 9.1.7. Hot Plug Messages
9.3. Receive Buffer Reordering x
9.3.1. Using Relaxed Ordering
10. Throughput Optimization x
10.1. Throughput of Posted Writes 10.2. Throughput of Non-Posted Reads
11. Design Implementation x
11.1. Making Analog QSF Assignments Using the Assignment Editor 11.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 11.3. Recommended Reset Sequence to Avoid Link Training Issues 11.4. SDC Timing Constraints
12. Additional Features x
12.1. Configuration over Protocol (CvP) 12.2. Autonomous Mode 12.3. ECRC
12.2. Autonomous Mode x
12.2.1. Enabling Autonomous Mode 12.2.2. Enabling CvP Initialization
12.3. ECRC x
12.3.1. ECRC on the RX Path 12.3.2. ECRC on the TX Path
14. Transceiver PHY IP Reconfiguration x
14.1. Connecting the Transceiver Reconfiguration Controller IP Core 14.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
15. Testbench and Design Example x
15.1. Endpoint Testbench 15.2. Root Port Testbench 15.3. Test Driver Module 15.4. Root Port Design Example 15.5. Root Port BFM Overview 15.6. BFM Procedures and Functions 15.7. Setting Up Simulation
15.1. Endpoint Testbench x
15.1.1. Endpoint Testbench for SR-IOV
15.5. Root Port BFM Overview x
15.5.1. BFM Memory Map 15.5.2. Configuration Space Bus and Device Numbering 15.5.3. Configuration of Root Port and Endpoint 15.5.4. Issuing Read and Write Transactions to the Application Layer
15.6. BFM Procedures and Functions x
15.6.1. ebfm_barwr Procedure 15.6.2. ebfm_barwr_imm Procedure 15.6.3. ebfm_barrd_wait Procedure 15.6.4. ebfm_barrd_nowt Procedure 15.6.5. ebfm_cfgwr_imm_wait Procedure 15.6.6. ebfm_cfgwr_imm_nowt Procedure 15.6.7. ebfm_cfgrd_wait Procedure 15.6.8. ebfm_cfgrd_nowt Procedure 15.6.9. BFM Configuration Procedures 15.6.10. BFM Shared Memory Access Procedures 15.6.11. BFM Log and Message Procedures 15.6.12. Verilog HDL Formatting Functions
15.6.9. BFM Configuration Procedures x
15.6.9.1. ebfm_cfg_rp_ep Procedure 15.6.9.2. ebfm_cfg_decode_bar Procedure
15.6.10. BFM Shared Memory Access Procedures x
15.6.10.1. Shared Memory Constants 15.6.10.2. shmem_write Task 15.6.10.3. shmem_read Function 15.6.10.4. shmem_display Verilog HDL Function 15.6.10.5. shmem_fill Procedure 15.6.10.6. shmem_chk_ok Function
15.6.11. BFM Log and Message Procedures x
15.6.11.1. ebfm_display Verilog HDL Function 15.6.11.2. ebfm_log_stop_sim Verilog HDL Function 15.6.11.3. ebfm_log_set_suppressed_msg_mask Task 15.6.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 15.6.11.5. ebfm_log_open Verilog HDL Function 15.6.11.6. ebfm_log_close Verilog HDL Function
15.6.12. Verilog HDL Formatting Functions x
15.6.12.1. himage1 15.6.12.2. himage2 15.6.12.3. himage4 15.6.12.4. himage8 15.6.12.5. himage16 15.6.12.6. dimage1 15.6.12.7. dimage2 15.6.12.8. dimage3 15.6.12.9. dimage4 15.6.12.10. dimage5 15.6.12.11. dimage6 15.6.12.12. dimage7
15.7. Setting Up Simulation x
15.7.1. Changing Between Serial and PIPE Simulation 15.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants 15.7.3. Viewing the Important PIPE Interface Signals 15.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 15.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations 15.7.6. Changing between the Hard and Soft Reset Controller
16. Debugging x
16.1. Hardware Bring-Up Issues 16.2. Link Training 16.3. Use Third-Party PCIe Analyzer 16.4. BIOS Enumeration Issues
16.2. Link Training x
16.2.1. Link Hangs in L0 State
C. Document Revision History x
C.1. Document Revision History of the Cyclone V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Cyclone V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts
7. Error Handling
8. IP Core Architecture
9. Transaction Layer Protocol (TLP) Details
10. Throughput Optimization
11. Design Implementation
12. Additional Features
13. Hard IP Reconfiguration
14. Transceiver PHY IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Frequently Asked Questions for PCI Express
B. Lane Initialization and Reversal
C. Document Revision History

4.7. Completion Side Band Signals

The following table describes the signals that comprise the completion side band signals for the Avalon-ST interface. The Cyclone V Hard IP for PCI Express provides a completion error interface that the Application Layer can use to report errors, such as programming model errors. When the Application Layer detects an error, it can assert the appropriate cpl_err bit to indicate what kind of error to log. If separate requests result in two errors, both are logged. The Hard IP sets the appropriate status bits for the errors in the Configuration Space, and automatically sends error messages in accordance with the PCI Express Base Specification. Note that the Application Layer is responsible for sending the completion with the appropriate completion status value for non-posted requests. Refer to Error Handling for information on errors that are automatically detected and handled by the Hard IP.

For a description of the completion rules, the completion header format, and completion status field values, refer to Section 2.2.9 of the PCI Express Base Specification.

Table 29.  Completion Signals for the Avalon-ST Interface

Signal

Direction

Description

cpl_err[6:0]

Input

Completion error. This signal reports completion errors to the Configuration Space. When an error occurs, the appropriate signal is asserted for one cycle.

  • cpl_err[0]: Completion timeout error with recovery. This signal should be asserted when a master-like interface has performed a non-posted request that never receives a corresponding completion transaction after the 50 ms timeout period when the error is correctable. The Hard IP automatically generates an advisory error message that is sent to the Root Complex.
  • cpl_err[1]: Completion timeout error without recovery. This signal should be asserted when a master-like interface has performed a non-posted request that never receives a corresponding completion transaction after the 50 ms time-out period when the error is not correctable. The Hard IP automatically generates a non-advisory error message that is sent to the Root Complex.
  • cpl_err[2]: Completer abort error. The Application Layer asserts this signal to respond to a non-posted request with a Completer Abort (CA) completion. The Application Layer generates and sends a completion packet with Completer Abort (CA) status to the requestor and then asserts this error signal to the Hard IP. The Hard IP automatically sets the error status bits in the Configuration Space register and sends error messages in accordance with the PCI Express Base Specification.
  • cpl_err[3]: Unexpected completion error. This signal must be asserted when an Application Layer master block detects an unexpected completion transaction. Many cases of unexpected completions are detected and reported internally by the Transaction Layer. For a list of these cases, refer to Transaction Layer Errors.
  • cpl_err[4]: Unsupported Request (UR) error for posted TLP. The Application Layer asserts this signal to treat a posted request as an Unsupported Request. The Hard IP automatically sets the error status bits in the Configuration Space register and sends error messages in accordance with the PCI Express Base Specification. Many cases of Unsupported Requests are detected and reported internally by the Transaction Layer. For a list of these cases, refer to Transaction Layer Errors.
  • cpl_err[5]: Unsupported Request error for non-posted TLP. The Application Layer asserts this signal to respond to a non-posted request with an Request (UR) completion. In this case, the Application Layer sends a completion packet with the Unsupported Request status back to the requestor, and asserts this error signal. The Hard IP automatically sets the error status bits in the Configuration Space Register and sends error messages in accordance with the PCI Express Base Specification. Many cases of Unsupported Requests are detected and reported internally by the Transaction Layer. For a list of these cases, refer to Transaction Layer Errors.
  • cpl_err[6]: Log header. If header logging is required, this bit must be set in the every cycle in which any of cpl_err[2], cpl_err[3], cpl_err[4], or cpl_err[5]is set. The Application Layer presents the header to the Hard IP by writing the following values to the following 4 registers using LMI before asserting cpl_err[6]:. The Application Layer presents the header to the Hard IP by writing the following values to the following 4 registers using LMI before asserting cpl_err[6]:
    • lmi_addr: 12'h81C, lmi_din: err_desc_func0[127:96]
    • lmi_addr: 12'h820, lmi_din: err_desc_func0[95:64]
    • lmi_addr: 12'h824, lmi_din: err_desc_func0[63:32]
    • lmi_addr: 12'h828, lmi_din: err_desc_func0[31:0]
cpl_pending[7:0]

Input

Completion pending. The Application Layer must assert this signal when a master block is waiting for completion, for example, when a transaction is pending. This is a level sensitive input. A bit is provided for each function, where bit 0 corresponds to function 0, and so on.
cpl_err_func[2:0]

Specifies which function is requesting the cpl_err. Must be asserted when cpl_err asserts. Due to clock-domain synchronization circuitry, cpl_err is limited to at most 1 assertion every 8 pld_clk cycles. Whenever cpl_err is asserted, cpl_err_func[2:0] should be updated in the same cycle.

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