Visible to Intel only — GUID: nik1410564936308
Ixiasoft
Visible to Intel only — GUID: nik1410564936308
Ixiasoft
Name |
Frequency |
Clock Domain |
---|---|---|
coreclkout_hip | 62.5, 125 or 250 MHz |
Avalon‑ST interface between the Transaction and Application Layers. |
pld_clk | pld_clk has a maximum frequency of 250 MHz and a minimum frequency that can be equal or more than the coreclkout_hip frequency, depending on the link width, link rate, and Avalon® interface width as indicated in the table for the Application Layer clock frequency above. |
Application and Transaction Layers. |
refclk |
100 or 125 MHz |
SERDES (transceiver). Dedicated free running input clock to the SERDES block. |
reconfig_xcvr_clk | 100 –125 MHz |
Transceiver Reconfiguration Controller. |
hip_reconfig_clk | 75–100 MHz |
Avalon‑MM interface for Hard IP dynamic reconfiguration interface which you can use to change the value of read‑only configuration registers at run‑time. This interface is optional. It is not required for Cyclone V devices. |