FIFO Intel® FPGA IP User Guide

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ID 683522
Date 3/29/2024
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Document Table of Contents
Document Table of Contents x
1. FIFO Intel® FPGA IP User Guide
1. FIFO Intel® FPGA IP User Guide x
1.1. Configuration Methods 1.2. Specifications 1.3. FIFO Functional Timing Requirements 1.4. SCFIFO ALMOST_EMPTY Functional Timing 1.5. FIFO Output Status Flag and Latency 1.6. FIFO Metastability Protection and Related Options 1.7. FIFO Synchronous Clear and Asynchronous Clear Effect 1.8. SCFIFO and DCFIFO Show-Ahead Mode 1.9. Different Input and Output Width 1.10. DCFIFO Timing Constraint Setting 1.11. Coding Example for Manual Instantiation 1.12. Design Example 1.13. Gray-Code Counter Transfer at the Clock Domain Crossing 1.14. Guidelines for Embedded Memory ECC Feature 1.15. FIFO Intel® FPGA IP User Guide Archives 1.16. Document Revision History for the FIFO Intel® FPGA IP User Guide
1.2. Specifications x
1.2.1. Verilog HDL Prototype 1.2.2. VHDL Component Declaration 1.2.3. VHDL LIBRARY-USE Declaration 1.2.4. FIFO Signals 1.2.5. FIFO Parameter Settings
1.7. FIFO Synchronous Clear and Asynchronous Clear Effect x
1.7.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
1.10. DCFIFO Timing Constraint Setting x
1.10.1. Embedded Timing Constraint 1.10.2. User Configurable Timing Constraint
1.10.2. User Configurable Timing Constraint x
1.10.2.1. SDC Commands
1. FIFO Intel® FPGA IP User Guide

1.5. FIFO Output Status Flag and Latency

The main concern in most FIFO design is the output latency of the read and write status signals.
Table 5.  Output Latency of the Status Flags for SCFIFOThis table shows the output latency of the write signal (wrreq) and read signal (rdreq) for the SCFIFO according to the different output modes and optimization options.
Output Mode Optimization Option 9 Output Latency (in number of clock cycles) 10
Normal 11 Speed wrreq / rdreq to full: 1
wrreq to empty: 2
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
rdreq to q[]: 1
Area wrreq / rdreq to full: 1
wrreq / rdreq to empty : 1
wrreq / rdreq to usedw[] : 1
rdreq to q[]: 1
Show-ahead 11 Speed wrreq / rdreq to full: 1
wrreq to empty: 3
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
wrreq to q[]: 3
rdreq to q[]: 1
Area wrreq / rdreq to full: 1
wrreq to empty: 2
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
wrreq to q[]: 2
rdreq to q[]: 1
Table 6.  ALM Implemented RAM Mode for SCFIFO and DCFIFO
Output Mode Optimization Option 12 Output Latency (in number of clock cycles) 13
Normal 14 Speed wrreq / rdreq to full: 1
wrreq to empty: 1
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
rdreq to q[]: 1
Area wrreq / rdreq to full: 1
wrreq / rdreq to empty : 1
wrreq / rdreq to usedw[] : 1
rdreq to q[]: 1
Show-ahead 14 Speed wrreq / rdreq to full: 1
wrreq to empty: 1
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
wrreq to q[]: 1
rdreq to q[]: 1
Area wrreq / rdreq to full: 1
wrreq to empty: 1
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
wrreq to q[]: 1
rdreq to q[]: 1
Table 7.  Output Latency of the Status Flag for the DCFIFO This table shows the output latency of the write signal (wrreq) and read signal (rdreq) for the DCFIFO.
Output Latency (in number of clock cycles) 15
wrreq to wrfull: 1 wrclk
wrreq to rdfull: 2 wrclk cycles + following n rdclk 16
wrreq to wrempty: 1 wrclk
wrreq to rdempty: 2 wrclk 17 + following n rdclk 17
wrreq to wrusedw[]: 2 wrclk
wrreq to rdusedw[]: 2 wrclk + following n + 1 rdclk 17
wrreq to q[]: 1 wrclk + following 1 rdclk 17
rdreq to rdempty: 1 rdclk
rdreq to wrempty: 1 rdclk + following n wrclk 17
rdreq to rfull: 1 rdclk
rdreq to wrfull: 1 rdclk + following n wrclk 17
rdreq to rdusedw[]: 2 rdclk
rdreq to wrusedw[]: 1 rdclk + following n + 1 wrclk 17
rdreq to q[]: 1 rdclk
9 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON. Setting the parameter to OFF is equivalent to area optimization.
10 The information of the output latency is applicable for Stratix® and Cyclone® series only. It may not be applicable for legacy devices such as the APEX® and FLEX® series.
11 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode, the parameter is set to ON.
12 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON. Setting the parameter to OFF is equivalent to area optimization.
13 The information of the output latency is applicable for Stratix® and Cyclone® series only. It may not be applicable for legacy devices such as the APEX® and FLEX® series.
14 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode, the parameter is set to ON.
15 The output latency information is only applicable for Arria® ® GX, Stratix® , and Cyclone® series.
16 The number of n cycles for rdclk and wrclk is equivalent to the number of synchronization stages and are related to the WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE parameters. For more information about how the actual synchronization stage (n) is related to the parameters set for different target device, refer to FIFO Metastability Protection and Related Options.
17 This is applied only to Show-ahead output modes. Show-ahead output mode is equivalent to setting the LPM_SHOWAHEAD parameter to ON.
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