FIFO Intel® FPGA IP User Guide

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ID 683522
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. FIFO Intel® FPGA IP User Guide
1. FIFO Intel® FPGA IP User Guide x
1.1. Configuration Methods 1.2. Specifications 1.3. FIFO Functional Timing Requirements 1.4. SCFIFO ALMOST_EMPTY Functional Timing 1.5. FIFO Output Status Flag and Latency 1.6. FIFO Metastability Protection and Related Options 1.7. FIFO Synchronous Clear and Asynchronous Clear Effect 1.8. SCFIFO and DCFIFO Show-Ahead Mode 1.9. Different Input and Output Width 1.10. DCFIFO Timing Constraint Setting 1.11. Coding Example for Manual Instantiation 1.12. Design Example 1.13. Gray-Code Counter Transfer at the Clock Domain Crossing 1.14. Guidelines for Embedded Memory ECC Feature 1.15. FIFO Intel® FPGA IP User Guide Archives 1.16. Document Revision History for the FIFO Intel® FPGA IP User Guide
1.2. Specifications x
1.2.1. Verilog HDL Prototype 1.2.2. VHDL Component Declaration 1.2.3. VHDL LIBRARY-USE Declaration 1.2.4. FIFO Signals 1.2.5. FIFO Parameter Settings
1.7. FIFO Synchronous Clear and Asynchronous Clear Effect x
1.7.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
1.10. DCFIFO Timing Constraint Setting x
1.10.1. Embedded Timing Constraint 1.10.2. User Configurable Timing Constraint
1.10.2. User Configurable Timing Constraint x
1.10.2.1. SDC Commands
1. FIFO Intel® FPGA IP User Guide

1.1. Configuration Methods

Table 1.  Configuration MethodsYou can configure and build the FIFO Intel® FPGA IP core with methods shown in the following table.
Method Description
Using the FIFO parameter editor. Altera recommends using this method to build your FIFO Intel® FPGA IP core. It is an efficient way to configure and build the FIFO Intel® FPGA IP core. The FIFO parameter editor provides options that you can easily use to configure the FIFO Intel® FPGA IP core.

You can access the FIFO Intel® FPGA IP core parameter editor in Basic Functions > On Chip Memory > FIFO of the IP catalog.1

Manually instantiating the FIFO Intel® FPGA IP core. Use this method only if you are an expert user. This method requires that you know the detailed specifications of the IP core. You must ensure that the input and output ports used, and the parameter values assigned are valid for the FIFO Intel® FPGA IP core you instantiate for your target device.
Related Information
1 Do not use dcfifo or scfifo as the entity name for your FIFO Platform Designer system.
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