FIFO Intel® FPGA IP User Guide

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ID 683522
Date 3/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. FIFO Intel® FPGA IP User Guide
1. FIFO Intel® FPGA IP User Guide x
1.1. Configuration Methods 1.2. Specifications 1.3. FIFO Functional Timing Requirements 1.4. SCFIFO ALMOST_EMPTY Functional Timing 1.5. FIFO Output Status Flag and Latency 1.6. FIFO Metastability Protection and Related Options 1.7. FIFO Synchronous Clear and Asynchronous Clear Effect 1.8. SCFIFO and DCFIFO Show-Ahead Mode 1.9. Different Input and Output Width 1.10. DCFIFO Timing Constraint Setting 1.11. Coding Example for Manual Instantiation 1.12. Design Example 1.13. Gray-Code Counter Transfer at the Clock Domain Crossing 1.14. Guidelines for Embedded Memory ECC Feature 1.15. FIFO Intel® FPGA IP User Guide Archives 1.16. Document Revision History for the FIFO Intel® FPGA IP User Guide
1.2. Specifications x
1.2.1. Verilog HDL Prototype 1.2.2. VHDL Component Declaration 1.2.3. VHDL LIBRARY-USE Declaration 1.2.4. FIFO Signals 1.2.5. FIFO Parameter Settings
1.7. FIFO Synchronous Clear and Asynchronous Clear Effect x
1.7.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
1.10. DCFIFO Timing Constraint Setting x
1.10.1. Embedded Timing Constraint 1.10.2. User Configurable Timing Constraint
1.10.2. User Configurable Timing Constraint x
1.10.2.1. SDC Commands
1. FIFO Intel® FPGA IP User Guide

1.16. Document Revision History for the FIFO Intel® FPGA IP User Guide

Document Version Quartus® Prime Version Changes
2024.03.29 18.0 Changed DISABLE_EMBEDDED_TIMING_CONSTRAINT to DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT for lpm_hint parameter in the FIFO Parameter Settings.
2023.11.17 18.0
  • Updated Table: Device Family Support for Width Ratios and added links to Agilex™ 7 Embedded Memory User Guide and Stratix® 10 Embedded Memory User Guide in Different Input and Output Width topic.
  • Updated document to the latest branding standards.
  • Made editorial edits throughout the document.
2023.04.14 18.0
  • Added links to Agilex™ 7 Embedded Memory User Guide and Stratix® 10 Embedded Memory User Guide in FIFO Intel® FPGA IP User Guide topic.
  • Added note in FIFO Synchronous Clear and Asynchronous Clear Effect.
  • Added footnote in Table: Asynchronous Clear in DCFIFO.
  • Added Valid Width Ratio for Stratix® 10 and Agilex™ 7 devices in Table: Device Family Support for Width Ratios.
2022.09.15 18.0 Fixed a broken KDB link in DCFIFO Timing Constraint Setting topic.
2020.12.14 18.0 Updated the description in the Gray-Code Counter Transfer at the Clock Domain Crossing topic of the FIFO section.
2019.11.21 18.0
  • Added lpm_hint to Table: FIFO Parameters.
  • Updated the description in the Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO section.
  • Remove references to Stratix® 10 devices throughout the document. Refer to the FIFO Intel® FPGA IP section of the Stratix® 10 Embedded Memory User Guide for more information.
2018.09.24 18.0
  • Updated Table: Input and Output Ports Description to include a note for usedw, wrusedw, and rdusedw ports.
  • Updated Table: FIFO Parameters to update the footnotes for lpm_widthu_r, delay_wrusedw, read_aclr_synch, and almost_empty_value.
2018.08.01 18.0 Updated the DCFIFO Timing Constraint Setting topic to add a note to recommend selecting the Generate SDC File and disable embedded timing constraint option for high frequency DCFIFO design.
2018.07.02 18.0 Updated the VHDL LIBRARY-USE Declaration topic to correct the VHDL Library declaration example from USE altera_mf_altera_mf_components.all; to USE altera_mf.altera_mf_components.all;.
2018.05.07 18.0
  • Renamed the document as FIFO Intel FPGA IP User Guide.
  • Renamed "SCFIFO and DCFIFO" IP cores to "FIFO Intel FPGA IP" core as per Intel rebranding.
  • Updated the description for ram_block_type in the FIFO Parameters topic.
  • Updated Table: Device Family Support for Width Ratios to include valid width ratios for Stratix® 10 devices.
  • Added a note to FIFO Synchronous Clear and Asynchronous Clear Effect topic to clarify that for Intel Stratix 10 devices, asserting aclr or sclr upon power-up guarantee correct functionality.
  • Updated the note in Table: DCFIFO Timing Constraint Setting Parameter in Quartus® Prime Software.
  • Updated Guidelines for Embedded Memory ECC Feature topic.
  • Updated Figure: ECC Option in FIFO Intel FPGA IP GUI.
  • Updated for latest branding standards.
  • Made editorial updates throughout the document.
Date Version Changes
November 2017 2017.11.06
  • Added support for Stratix® 10, Cyclone® 10 LP, and Cyclone® 10 GX devices.
  • Updated the LE Implemented RAM Mode for SCFIFO and DCFIFO table to correct output latency for wrreq to empty.
  • Updated the SCFIFO and DCFIFO Parameters to include add_usedw_msb_bit register signal.
  • Updated for latest branding standards.
May 2017 2017.05.08
  • Rebranded as Intel.
  • Added a table listing the device family support for width ratio in the Different Input and Output Width topic.
  • Minor typographical corrections and stylistic changes.
August 2016 2016.08.29
  • Added note to Configuration Methods stating that scfifo and dcfifo cannot ne used for FIFO Qsys entity name.
  • Added note to almost_empty in SCFIFO and DCFIFO Signals table.
  • Added SCFIFO ALMOST_EMPTY Functional Timing section.
May 2016 2016.05.30 Added note about using skew_report.tcl if Embedded Timing Constraint is used and report_max_skew.
May 2016 2016.05.02
  • Added list of user configurable constraint commands and descriptions in Constrain Commands.
  • Added timing constraints for mixed-width DCFIFO.
  • Upgraded design example with ECC feature enabled.
  • Added Guidelines for Embedded Memory ECC Feature section.
  • Removed 32-bit width FIFO limitation for eccstatus signal and enable_ecc parameter.
  • Added FIFO IP core parameter editor directory in IP catalog in Configuration Methods section.
November 2015 2015.11.02
  • Added User Configurable Timing Constraint.
  • Added DCFIFO Timing Constraint Setting.
  • Renamed Constraint Settings to Embedded Constraint Settings.
  • Moved normal and show-ahead description from parameter table to SCFIFO and DCFIFO Show-Ahead Mode subsection.
  • Added normal and show-ahead waveform for comparison.
  • Added eccstatus port in block diagram and port table list available in Quartus II 15.1 release.
  • Added enable_ecc parameter in SCFIFO and DCFIFO Parameters.
  • Updated Verilog HDL prototype directory.
  • Corrected lpm_numwords register equation.
  • Updated Example 1: Verilog HDL Coding Example to Instantiate the DCFIFO IP Core.
December 2014 2014.12.17
  • Clarified that there are no minimum number of clock cycles for aclr signals that must remain active.
  • Added Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO Megafunction section.
  • Removed a note about ignoring any recovery and removal violation reported in the TimeQuest timing analyzer that represent transfers from the aclr to the read side clock domain in Synchronous Clear and Asynchronous Clear Effect section.
May 2013 8.2
  • Updated Table 8 on page 20 to state that both the read and write pointers reset to zero upon assertion of either the sclr or aclr signal.
  • Updated Table 1 on page 7 to note that the wrusedw, rdusedw, wrfull, rdfull wrempty and rdempty values are subject to the latencies listed in Table 5 on page 18.
August 2012 8.1
  • Included a link to skew_report.tcl “Gray-Code Counter Transfer at the Clock Domain Crossing” on page 29.
August 2012 8.0
  • Updated “DCFIFO” on page 3, “Ports Specifications” on page 6, “Functional Timing Requirements” on page 14, “Synchronous Clear and Asynchronous Clear Effect” on page 20.
  • Updated Table 1 on page 7, Table 2 on page 10, Table 9 on page 21.
  • Added Table 4 on page 16.
  • Renamed and updated “DCFIFO Clock Domain Crossing Timing Violation” to “Gray-Code Counter Transfer at the Clock Domain Crossing” on page 29.
February 2012 7.0
  • Updated the notes for Table 4 on page 16.
  • Added the “DCFIFO Clock Domain Crossing Timing Violation” section.
September 2010 6.2 Added prototype and component declarations.
January 2010 6.1
  • Updated “Functional Timing Requirements” section.
  • Minor changes to the text.
September 2009 6.0
  • Replaced “FIFO Megafunction Features” section with “Configuration Methods”.
  • Updated “Input and Output Ports”.
  • Added “Parameter Specifications”, “Output Status Flags and Latency”, “Metastability Protection and Related Options”, “Constraint Settings”, “Coding Example for Manual Instantiation”, and “Design Example”.
February 2009 5.1 Minor update in Table 8 on page 17.
January 2009 5.0 Complete re-write of the user guide.
May 2007 4.0
  • Added support for Arria GX devices.
  • Updated for new GUI.
  • Added six design examples in place of functional description.
  • Reorganized and updated Chapter 3 to have separate tables for the SCFIFO and DCFIFO megafunctions.
  • Added Referenced Documents section.
March 2007 3.3
  • Minor content changes, including adding Stratix  III and Cyclone III information
  • Re-took screenshots for software version 7.0
September 2005 3.2 Minor content changes.
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