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1.1. Configuration Methods
1.2. Specifications
1.3. FIFO Functional Timing Requirements
1.4. SCFIFO ALMOST_EMPTY Functional Timing
1.5. FIFO Output Status Flag and Latency
1.6. FIFO Metastability Protection and Related Options
1.7. FIFO Synchronous Clear and Asynchronous Clear Effect
1.8. SCFIFO and DCFIFO Show-Ahead Mode
1.9. Different Input and Output Width
1.10. DCFIFO Timing Constraint Setting
1.11. Coding Example for Manual Instantiation
1.12. Design Example
1.13. Gray-Code Counter Transfer at the Clock Domain Crossing
1.14. Guidelines for Embedded Memory ECC Feature
1.15. FIFO Intel® FPGA IP User Guide Archives
1.16. Document Revision History for the FIFO Intel® FPGA IP User Guide
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1.10. DCFIFO Timing Constraint Setting
The FIFO parameter editor provides the timing constraint setting for the DCFIFO function.
| Parameter | Description |
|---|---|
| Generate SDC File and disable embedded timing constraint 26 | Allows you to bypass embedded timing constraints that uses set_false_path in the synchronization registers. A user configurable SDC file is generated automatically when DCFIFO is instantiated from the IP Catalog. New timing constraints consist of set_net_delay, set_max_skew, set_min_delay and set_max_delay are used to constraint the design properly.
Note: Altera recommends that you select this option for high frequency DCFIFO design to achieve timing closure. For more information, refer to User Configurable Timing Constraint.
|
26 Parameter is available in Quartus® Prime software version 15.1 and later and applicable for Arria® 10 and Cyclone® 10 GX devices only. You can disable the embedded timing constraint with QSF setting in prior Quartus® Prime versions and other devices. Refer to KDB link on the QSF assignment setting.