Intel® FPGA SDK for OpenCL™ Pro Edition: Best Practices Guide

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Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction to Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide 2. Reviewing Your Kernel's report.html File 3. OpenCL Kernel Design Concepts 4. OpenCL Kernel Design Best Practices 5. Profiling Your Kernel to Identify Performance Bottlenecks 6. Strategies for Improving Single Work-Item Kernel Performance 7. Strategies for Improving NDRange Kernel Data Processing Efficiency 8. Strategies for Improving Memory Access Efficiency 9. Strategies for Optimizing FPGA Area Usage 10. Strategies for Optimizing Intel® Stratix® 10 OpenCL Designs 11. Strategies for Improving Performance in Your Host Application 12. Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide Archives A. Document Revision History for the Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide
1. Introduction to Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide x
1.1. FPGA Overview 1.2. Pipelines 1.3. Single Work-Item Kernel versus NDRange Kernel
2. Reviewing Your Kernel's report.html File x
2.1. High-Level Design Report Layout 2.2. Reviewing the Summary Report 2.3. Viewing Throughput Bottlenecks in the Design 2.4. Using Views 2.5. Analyzing Throughput 2.6. Reviewing Area Information 2.7. Optimizing an OpenCL Design Example Based on Information in the HTML Report 2.8. Accessing HLD FPGA Reports in JSON Format
2.4. Using Views x
2.4.1. Features of the System Viewer 2.4.2. Features of the Kernel Memory Viewer 2.4.3. Features of the Schedule Viewer
2.4.1. Features of the System Viewer x
2.4.1.1. Reviewing System Information 2.4.1.2. Reviewing Global Memory Information 2.4.1.3. Reviewing Block Information 2.4.1.4. Reviewing Cluster Information
2.5. Analyzing Throughput x
2.5.1. Reviewing Loop Information
2.6. Reviewing Area Information x
2.6.1. Area Report Message for Board Interface 2.6.2. Area Report Message for Function Overhead 2.6.3. Area Report Message for State 2.6.4. Area Report Message for Feedback 2.6.5. Area Report Messages for Private Variable Storage
2.6.5. Area Report Messages for Private Variable Storage x
2.6.5.1. Area Report Message for Constant Memory
3. OpenCL Kernel Design Concepts x
3.1. Kernels 3.2. Global Memory Interconnect 3.3. Local Memory 3.4. Loops in a Single Work-Item Kernel 3.5. Channels 3.6. Load-Store Units
3.3. Local Memory x
3.3.1. Changing the Memory Access Pattern Example
3.4. Loops in a Single Work-Item Kernel x
3.4.1. Trade-Off Between Initiation Interval and Maximum Frequency 3.4.2. Loop-Carried Dependencies that Affect the Initiation Interval of a Loop 3.4.3. Nested Loops 3.4.4. Loop Speculation 3.4.5. Loop Fusion 3.4.6. Loop Bottlenecks
3.4.3. Nested Loops x
3.4.3.1. Reducing the Area Consumed by Nested Loops Using loop_coalesce
3.6. Load-Store Units x
3.6.1. Load-Store Unit Types 3.6.2. Load-Store Unit Modifiers 3.6.3. Controlling the Load-Store Units 3.6.4. When to Use Each LSU
4. OpenCL Kernel Design Best Practices x
4.1. Transferring Data Via Intel® FPGA SDK for OpenCL™ Channels or OpenCL Pipes 4.2. Unrolling Loops 4.3. Optimizing Floating-Point Operations 4.4. Allocating Aligned Memory 4.5. Aligning a Struct with or without Padding 4.6. Maintaining Similar Structures for Vector Type Elements 4.7. Avoiding Pointer Aliasing 4.8. Avoid Expensive Functions 4.9. Avoiding Work-Item ID-Dependent Backward Branching
4.1. Transferring Data Via Intel® FPGA SDK for OpenCL™ Channels or OpenCL Pipes x
4.1.1. Characteristics of Channels and Pipes 4.1.2. Execution Order for Channels and Pipes 4.1.3. Optimizing Buffer Inference for Channels or Pipes 4.1.4. Best Practices for Channels and Pipes
4.3. Optimizing Floating-Point Operations x
4.3.1. Floating-Point versus Fixed-Point Representations
5. Profiling Your Kernel to Identify Performance Bottlenecks x
5.1. Best Practices for Profiling Your Kernel 5.2. Instrumenting the Kernel Pipeline with Performance Counters (-profile) 5.3. Obtaining Profiling Data During Runtime 5.4. Reducing Area Resource Use While Profiling 5.5. Temporal Performance Collection 5.6. Performance Data Types 5.7. Interpreting the Profiling Information 5.8. Profiler Analyses of Example OpenCL Design Scenarios 5.9. Intel® FPGA Dynamic Profiler for OpenCL™ Limitations
5.3. Obtaining Profiling Data During Runtime x
5.3.1. Invoking the Profiler Runtime Wrapper 5.3.2. Viewing Profiling Data Using Intel® VTune™ Profiler
5.3.1. Invoking the Profiler Runtime Wrapper x
5.3.1.1. Splitting Execution and Data Post Processing
5.5. Temporal Performance Collection x
5.5.1. Profiling Autorun Kernels
5.7. Interpreting the Profiling Information x
5.7.1. Stall, Occupancy, Bandwidth 5.7.2. Stalling Channels 5.7.3. Channel Depths
5.8. Profiler Analyses of Example OpenCL Design Scenarios x
5.8.1. High Stall Percentage 5.8.2. Low Occupancy Percentage 5.8.3. High Stall and High Occupancy Percentages 5.8.4. No Stalls, Low Occupancy Percentage, and Low Bandwidth 5.8.5. No Stalls, High Occupancy Percentage, and Low Bandwidth 5.8.6. High Stall and Low Occupancy Percentages
6. Strategies for Improving Single Work-Item Kernel Performance x
6.1. Addressing Single Work-Item Kernel Dependencies Based on Optimization Report Feedback 6.2. Good Design Practices for Single Work-Item Kernel
6.1. Addressing Single Work-Item Kernel Dependencies Based on Optimization Report Feedback x
6.1.1. Removing Loop-Carried Dependency 6.1.2. Relaxing Loop-Carried Dependency 6.1.3. Transferring Loop-Carried Dependency to Local Memory 6.1.4. Relaxing Loop-Carried Dependency by Inferring Shift Registers 6.1.5. Removing Loop-Carried Dependencies Caused by Accesses to Memory Arrays
7. Strategies for Improving NDRange Kernel Data Processing Efficiency x
7.1. Specifying a Maximum Work-group Size or a Required Work-Group Size 7.2. Kernel Vectorization 7.3. Multiple Compute Units 7.4. Combination of Compute Unit Replication and Kernel SIMD Vectorization 7.5. Reviewing Kernel Properties and Loop Unroll Status in the HTML Report
7.3. Multiple Compute Units x
7.3.1. Compute Unit Replication versus Kernel SIMD Vectorization
8. Strategies for Improving Memory Access Efficiency x
8.1. General Guidelines on Optimizing Memory Accesses 8.2. Optimize Global Memory Accesses 8.3. Performing Kernel Computations Using Constant, Local or Private Memory 8.4. Improving Kernel Performance by Banking the Local Memory 8.5. Optimizing Accesses to Local Memory by Controlling the Memory Replication Factor 8.6. Minimizing the Memory Dependencies for Loop Pipelining 8.7. Static Memory Coalescing
8.2. Optimize Global Memory Accesses x
8.2.1. Contiguous Memory Accesses 8.2.2. Manual Partitioning of Global Memory 8.2.3. Optimizing for Two or More Banks of Global Memory
8.2.2. Manual Partitioning of Global Memory x
8.2.2.1. Heterogeneous Memory Buffers
8.3. Performing Kernel Computations Using Constant, Local or Private Memory x
8.3.1. Constant Cache Memory 8.3.2. Preloading Data to Local Memory 8.3.3. Storing Variables and Arrays in Private Memory
8.4. Improving Kernel Performance by Banking the Local Memory x
8.4.1. Optimizing the Geometric Configuration of Local Memory Banks Based on Array Index
9. Strategies for Optimizing FPGA Area Usage x
9.1. Compilation Considerations 9.2. Board Variant Selection Considerations 9.3. Memory Access Considerations 9.4. Arithmetic Operation Considerations 9.5. Data Type Selection Considerations
10. Strategies for Optimizing Intel® Stratix® 10 OpenCL Designs x
10.1. Reducing Channel Overhead 10.2. Optimizing Loop Control 10.3. Simplifying Memory Access to Local Memories 10.4. On-Chip Storage of Reused Data 10.5. Optimizing Data Path Control 10.6. Creating RTL Modules
10.1. Reducing Channel Overhead x
10.1.1. Reducing the Number of Kernels 10.1.2. Using a Single Kernel to Describe Systolic Arrays 10.1.3. Using Non-Blocking Channels
10.2. Optimizing Loop Control x
10.2.1. Simplifying Loop-Carried Dependencies in Intel® Stratix® 10 OpenCL Designs
10.6. Creating RTL Modules x
10.6.1. Reset Recommendations
11. Strategies for Improving Performance in Your Host Application x
11.1. Multi-Threaded Host Application 11.2. Utilizing Hardware Kernel Invocation Queue
11.2. Utilizing Hardware Kernel Invocation Queue x
11.2.1. Double Buffered Host Application Utilizing Kernel Invocation Queue
1. Introduction to Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide
2. Reviewing Your Kernel's report.html File
3. OpenCL Kernel Design Concepts
4. OpenCL Kernel Design Best Practices
5. Profiling Your Kernel to Identify Performance Bottlenecks
6. Strategies for Improving Single Work-Item Kernel Performance
7. Strategies for Improving NDRange Kernel Data Processing Efficiency
8. Strategies for Improving Memory Access Efficiency
9. Strategies for Optimizing FPGA Area Usage
10. Strategies for Optimizing Intel® Stratix® 10 OpenCL Designs
11. Strategies for Improving Performance in Your Host Application
12. Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide Archives
A. Document Revision History for the Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide

A. Document Revision History for the Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide

Document Version Intel® Quartus® Prime Version Changes
2021.12.13 21.4
  • Maintenance release.
2021.10.04 21.3
  • Maintenance release.
2021.06.21 21.2
  • Removed some outdated images and improved some of the descriptions in the Reviewing Your Kernel's report.html File chapter.
2021.03.29 21.1
  • Updated the messages in Area Report Messages for Private Variable Storage.
  • Added a new section in Optimize Global Memory Accesses about how to calculate the global memory bandwidth use.
  • Added a new topic Reviewing Global Memory Information to describe the global memory view of the System Viewer in the report.html file.
  • Updated the topic Features of the Schedule Viewer to include details about the dependency lines.
  • Changed the Graph Viewer report name to System Viewer.
2020.12.14 20.4 Maintenance release.
2020.09.28 20.3
  • Minor update to Loop Fusion topic about trip count condition relaxation.
  • Added a topic Viewing Throughput Bottlenecks in the Design.
  • Added a new topic Loop Bottlenecks.
  • Updated Accessing HLD FPGA Reports in JSON Format and High-level Design Report Layout topics to include Bottlenecks viewer.
  • Made minor update in Profiling Your Kernel to Identify Performance Bottlenecks and Best Practices for Profiling Your Kernel.
  • In Instrumenting the Kernel Pipeline with Performance Counters (-profile), removed a bullet point about running the host application from the local disk.
  • Updated the topic title and description of Invoking the Profiler Runtime Wrapper
  • Updated the Profiling Autorun Kernels topic completely.
  • Renamed the topic Intel® VTune™ Profiler as Viewing Profiling Data Using Intel® VTune™ Profiler and made minor update to the topic description.
  • In the Performance Data Types topic, updated the description, added two new information types in the Types of Performance Data table, removed the Types of Information of table, and added a note.
  • Made minor update in the Interpreting the Profiling Information topic description.
  • Made minor update in the Stall, Occupancy, Bandwidth topic description.
  • Removed information about the Intel FPGA dynamic profiler for OpenCL and the screenshot in High Stall Percentage topic.
  • Minor update to the topic titles of No Stalls, Low Occupancy Percentage, and Low Bandwidth and No Stalls, High Occupancy Percentage, and Low Bandwidthand updated their images.
  • In Intel FPGA Dynamic Profiler for OpenCL Limitations, removed a limitation and added a new limitation.
  • Removed the following topics:
    • Intel FPGA Dynamic Profiler for OpenCL GUI
    • Launching the Intel FPGA Dynamic Profiler for OpenCL GUI (report)
    • Source Code Tab
    • Tool Tip Options
    • Kernel Execution Tab
    • Autorun Captures Tab
    • Activity
    • Cache Hit
    • Low Bandwidth Efficiency
    • Autorun Profiler Data
  • Added the following new topics:
    • Reducing Area Resource Usage While Profiling
    • Obtaining Profiling Data During Runtime
    • Splitting Execution and Data Post Processing
    • Temporal Performance Collection
    • Channel Depths
2020.06.22 20.2
  • Updated a guideline about the use of local_mem_size attribute in Preloading Data to Local Memory.
  • Added scheduler's behavior in different scenarios to Reviewing Loop Information.
  • Removed Out of Order Loop Iterations section in Nested Loops topic.
  • Made minor update regarding the support for double pumping in Intel® Stratix® 10 devices in Simplifying Memory Access to Local Memories
2020.04.13 20.1
  • Updated the topic title and entire topic of Optimizing for Two or More Banks of Global Memory.
  • Updated the entire Reviewing Your Kernel's report.html File chapter.
  • Removed the Reviewing fMAX II Information topic since Fmax II report is deprecated. See Loop Analysis report.
  • Added fmax related information to the Loop Analysis report.
  • Added a new topic Performance Data Types.
  • Added a new topic Intel VTune Profiler.
  • Added a new topic Invoking the Profiler Runtime Wrapper to Obtain Profiling .
  • Made minor updates and reorganized the existing topics of Profiling Your Kernel to Identify Performance Bottlenecks chapter.
  • Added a new topic Loop Fusion.
  • Updated the Loops in a Single Work-Item Kernel topic completely.
  • Updated the Loop-Carried Dependencies that Affect the Initiation Interval of a Loop topic completely.
  • Updated the Trade-Off Between Initiation Interval and Maximum Frequency topic completely.
2019.09.30 19.3
  • Updated the topic Load-Store Units completely.
    • Removed Streaming Load-Store Units, Semi-Streaming Load-Store Units, and Global Infrequent Load-Store Units sections.
    • Changed Local-Pipelined Load-Store Units as Pipelined Load-Store Units and added more information within this section.
    • Updated the code snippet in the Cached section.
    • Added new topics Controlling the Load-Store Units and When to Use Each LSU.
  • Updated the Optimizing Accesses to Local Memory by Controlling the Memory Replication Factor topic completely and replaced the code snippets.
  • Updated the Channels topic to include more information about the depth attribute.
  • Added a new topic about Schedule Viewer.
  • Minor updates in Reviewing Block Information and Reviewing Cluster Information topics.
  • Added a new topic Reviewing System Information and moved some of the existing instructions to this page.
  • Removed system view related information and images from the Features of the Graph Viewer topic and moved it to the Reviewing System Information topic.
  • Updated images in High Level Design Report Layout and Reviewing the Report Summary topics.
  • Made minor updates in Accessing HLD FPGA Reports in JSON Format topic.
2019.07.01 19.2
  • Added the following topics from the Intel® FPGA SDK for OpenCL™ Pro Edition Programming Guide in the Profiling Your Kernel to Identify Performance Bottlenecks:
    • Launching the GUI (report)
    • Instrumenting the Kernel Pipeline with Performance Counters (-profile)
    • Profiling Autorun Kernels
  • Removed the topic HTML Report: Area Report Messages and moved its subtopics under Reviewing Area Information.
  • In Reviewing Area Information, included a note about analyze-area from the Intel® FPGA SDK for OpenCL™ Pro Edition Programming Guide
  • System Viewer, Block Viewer and Cluster Viewer topics merged into the Graph Viewer report. Relevant topics and images were updated accordingly.
  • In Single Work-Item Kernel versus NDRange Kernel, accum_swg kernel code line 6 was updated.
2019.05.08 19.1
  • Updated Kernel Execution Tab since “Memory Copy (from device)” and “Memory Copy (to device)” are no longer supported.
  • Added document archives chapter.
2019.04.01 19.1
2018.09.24 18.1
2018.05.04 18.0
Table 21.   Intel® FPGA SDK for OpenCL™ Best Practices Guide Document Revision History
Date Version Changes
December 2017 2017.12.08
  • Added the following new topics:
    • Autorun Captures Tab
    • Autorun Profiler Data
November 2017 2017.11.06
May 2017 2017.05.08
December 2016 2016.12.02 Minor editorial modification.
October 2016 2016.10.31
  • Rebranded the Altera SDK for OpenCL to Intel® FPGA SDK for OpenCL™ .
  • Rebranded the Altera Offline Compiler to Intel® FPGA SDK for OpenCL™ Offline Compiler.
  • In Align a Struct with or without Padding, modified code snippets to correct the placement of attributes with respect to the struct declaration.
  • Added the topic Review Your Kernel's report.html File, with subtopics describing the HTML GUI, the various reports the GUI provides, and a walkthrough on how to leverage the information in the HTML report to optimize an OpenCL design example.
  • Changed Review Your Kernel's Area Report to Identify Inefficiencies in Resource Usage to HTML Report: Area Report Messages, and removed the following subsections:
    • Area Report Messages for Global Memory and Global Memory Interconnect
    • Area Report Messages for Local Memory
    • Area Report Messages for Channels
  • Added the topic HTML Report: Kernel Design Concepts, which includes subtopics on kernels, global memory interconnect, local memory, nested loops, loops in single work-item kernels, and channels.
  • In Interpreting the Profiling Information, reorganized the content and added the following:
    • Additional explanations on stall, occupancy, bandwidth, activity, and cache hit.
    • Suggestions on addressing unsatisfactory Profiler metrics.
  • In Addressing Single Work-Item Kernel Dependencies Based On Optimization Report Feedback, modified the figure Optimization Work Flow of a Single Work-Item Kernel to replace area report with HTML report.
  • Removed the Optimization Report section along with the associated subsections because the information is now part of the HTML report.
  • Changed Review Kernel Properties and Loop Unroll Status in the Optimization Report to Review Kernel Properties and Loop Unroll Status in the HTML Report because the optimization report is now part of the report.html file.
May 2016 2016.05.02
  • Added the topic Removing Loop-Carried Dependencies Caused by Accesses to Memory Arrays to introduce the ivdep pragma.
  • Under Strategies for Improving Memory Access Efficiency, added the following topics to explain how to use the numbanks and bankwidth kernel attributes to configure the geometry of local memory system:
    • Improve Kernel Performance by Banking the Local Memory
    • Optimize the Geometric Configuration of Local Memory Banks Based on Array Index
  • Under Strategies for Improving Memory Access Efficiency, added the topic Optimize Accesses to Local Memory by Controlling the Memory Replication Factor to explain the usage of the singlepump and doublepump kernel attributes.
  • Added information on the area report messages. Refer to the Review Your Kernel's Area Report to Identify Inefficiencies in Resource Usage section for more information.
  • Removed the Kernel-Specific Area Report section because it is replaced by the enhanced area report. Refer to the Review Your Kernel's Area Report to Identify Inefficiencies in Resource Usage section for more information.
  • Updated the subsections under Optimization Report to include the enhanced optimization report messages.
    • Added the Optimization Report Message for Speed-Limiting Constructs
  • Updated the subsections under Addressing Single Work-Item Kernel Dependencies Based on Optimization Report Feedback to include the enhanced optimization report messages.
  • Updated the figure Optimization Work Flow for a Single Work-Item Kernel to include steps on accessing the enhanced area report to review resource usage.
  • Under Strategies for Improving NDRange Kernel Data Processing Efficiency, added the Review Kernel Properties and Loop Unroll Status in the Optimization Report section.
November 2015 2015.11.02
  • Added the topic Multi-Threaded Host Application.
  • Added Caution note regarding memory barrier in Specify a Maximum Work-Group Size or a Required Work-Group Size.
May 2015 15.0.0
  • In Memory Access Considerations, added Caution note regarding performance degradation that might occur when declaring __constant pointer arguments in kernels targeting Cyclone® V devices.
  • In Good Design Practices for Single Work-Item Kernel, removed the Initialize Data Prior to Usage in a Loop section and added a Declare Variables in the Deepest Scope Possible section.
  • Added Removing Loop-Carried Dependency by Inferring Shift Registers. The topic discusses how, in single work-item kernels, inferring double precision floating-point array as a shift register can remove loop-carried dependencies.
  • Added Kernel-Specific Area Reports to show examples of kernel-specific .area files that the Altera Offline Compiler generates during compilation.
  • Renamed Transfer Data Via offline compiler Channels to Transfer Data Via offline compiler Channels or OpenCL Pipes and added the following:
    • More information on how channels can help improve kernel performance.
    • Information on OpenCL pipes.
  • Renamed Data Type Considerations to Data Type Selection Considerations.
December 2014 14.1.0
  • Reorganized the information flow in the Optimization Report Messages section to update report messages and the layout of the optimization report.
  • Included new optimization report messages detailing the reasons for unsuccessful and suboptimal pipelined executions.
  • Added the Optimization Report Messages for Simplified Analysis of a Complex Design subsection under Optimization Report Messages to describe new report message for simplified kernel analysis.
  • Renamed Using Feedback from the Optimization Report to Address Single Work-Item Kernels Dependencies to Addressing Single Work-Item Kernel Dependencies Based on Optimization Report Feedback.
  • Added the Transferring Loop-Carried Dependency to Local Memory subsection under Addressing Single Work-Item Kernel Dependencies Based on Optimization Report Feedback to describe new strategy for resolving loop-carried dependency.
  • Updated the Resource-Driven Optimization and Compilation Considerations sections to reflect the deprecation of the -O3 and --util <N> Altera® Offline Compiler (offline compiler) command options.
  • Consolidated and simplified the Heterogeneous Memory Buffers and Host Application Modifications for Heterogeneous Memory Accesses sections.
  • Added the section Align a Struct and Remove Padding between Struct Fields.
  • Removed the section Ensure 4-Byte Alignment to All Data Structures.
  • Modified the figure Single Work-Item Optimization Work Flow to include emulation and profiling.
June 2014 14.0.0
  • Renamed document as the Intel® FPGA SDK for OpenCL™ Best Practices Guide.
  • Reorganized information flow.
  • Renamed Good Design Practices to Good OpenCL Kernel Design Practices.
  • Added channels information in Transfer data via offline compiler Channels.
  • Added profiler information in Profile Your Kernel to Identify Performance Bottlenecks.
  • Added the section Single Work-Item Kernel Versus NDRange Kernel.
  • Updated Single Work-Item Execution section.
  • Removed Performance Warning Messages section.
  • Renamed Single Work-Item Kernel Programming Considerations to Good Design Practices for Single Work-Item Kernel.
  • Added the section Strategies for Improving Single Work-Item Kernel Performance.
  • Renamed Optimization of Data Processing Efficiency to Strategies for Improving NDRange Kernel Data Processing Efficiency.
  • Removed Resource Sharing section.
  • Renamed Floating-Point Operations to Optimize Floating-Point Operations.
  • Renamed Optimization of Memory Access Efficiency to Strategies for Improving Memory Access Efficiency.
  • Updated Manual Partitioning of Global Memory section.
  • Added the section Strategies for Optimizing FPGA Area Usage.
December 2013 13.1.1
  • Updated the section Specify a Maximum Work-Group Size or a Required Work-Group Size.
  • Added the section Heterogeneous Memory Buffers.
  • Updated the section Single Work-Item Execution.
  • Added the section Performance Warning Messages.
  • Updated the section Single Work-Item Kernel Programming Considerations .
November 2013 13.1.0
  • Reorganized information flow.
  • Updated the section Intel® FPGA SDK for OpenCL™ Compilation Flow.
  • Updated the section Pipelines; inserted the figure Example Multistage Pipeline Diagram.
  • Removed the following figures:
    • Instruction Flow through a Five-Stage Pipeline Processor.
    • Vector Addition Kernel Compiled to an FPGA.
    • Effect of Kernel Vectorization on Array Summation.
    • Data Flow Implementation of a Four-Element Accumulation Kernel.
    • Data Flow Implementation of a Four-Element Accumulation Kernel with Loop Unrolled.
    • Complete Loop Unrolling.
    • Unrolling Two Loop Iterations.
    • Memory Master Interconnect.
    • Local Memory Read and Write Ports.
    • Local Memory Configuration.
  • Updated the section Good Design Practices.
  • Removed the following sections:
    • Predicated Execution.
    • Throughput Analysis.
    • Case Studies.
  • Updated and renamed Optimizing Data Processing Efficiency to Optimization of Data Processing Efficiency.
  • Renamed Replicating Compute Units versus Kernel SIMD Vectorization to Compute Unit Replication versus Kernel SIMD Vectorization.
  • Renamed Using num_compute_units and num_simd_work_items Together to Combination of Compute Unit Replication and Kernel SIMD Vectorization.
  • Updated and renamed Memory Streaming to Contiguous Memory Accesses.
  • Updated and renamed Optimizing Memory Access to General Guidelines on Optimizing Memory Accesses.
  • Updated and renamed Optimizing Memory Efficiency to Optimization of Memory Access Efficiency.
  • Inserted the subsection Single Work-Item Execution under Optimization of Memory Access Efficiency.
June 2013 13.0 SP1.0
  • Updated support status of OpenCL kernel source code containing complex exit paths.
  • Updated the figure Effect of Kernel Vectorization on Array Summation to correct the data flow between Store and Global Memory.
  • Updated content for the unroll pragma directive in the section Loop Unrolling.
  • Updated content of the Local Memory section.
  • Updated the figure Local Memories Transferring Data Blocks within Matrices A and B to correct the data transfer pattern in Matrix B.
  • Removed the figure Loop Unrolling with Vectorization.
  • Removed the section Optimizing Local Memory Bandwidth.
May 2013 13.0.1
  • Updated terminology. For example, pipeline is replaced with compute unit; vector lane is replaced with SIMD vector lane.
  • Added the following sections under Good Design Practices:
    • Preprocessor Macros.
    • Floating-Point versus Fixed-Point Representations.
    • Recommended Optimization Methodology.
    • Sequence of Optimization Techniques.
  • Updated code fragments.
  • Updated the figure Data Flow with Multiple Compute Units.
  • Updated the figure Compute Unit Replication versus Kernel SIMD Vectorization.
  • Updated the figure Optimizing Throughput Using Compute Unit Replication and SIMD Vectorization.
  • Updated the figure Memory Streaming.
  • Inserted the figure Local Memories Transferring Data Blocks within Matrices A and B.
  • Reorganized the flow of information. Number of figures, tables, and examples have been updated.
  • Included information on new kernel attributes: max_share_resources and num_share_resources .
May 2013 13.0.0
  • Updated pipeline discussion.
  • Updated case study code examples and results tables.
  • Updated figures.
November 2012 12.1.0 Initial release.
Level Two Title