V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

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ID 683514
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM DMA 3. Parameter Settings 4. Registers 5. Error Handling 6. PCI Express Protocol Stack 7. V-Series Avalon-MM DMA for PCI Express 8. Transceiver PHY IP Reconfiguration A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe B. V-Series Interface for PCIe Solutions User Guide Archive C. Document Revision History
1. Datasheet x
1.1. V-Series Avalon-MM DMA Interface for PCIe* Datasheet 1.2. Features 1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces for V-Series Devices 1.4. Release Information 1.5. V-Series Device Family Support 1.6. Design Examples 1.7. Debug Features 1.8. IP Core Verification 1.9. Resource Utilization 1.10. V-Series Recommended Speed Grades 1.11. Creating a Design for PCI Express
1.8. IP Core Verification x
1.8.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM DMA x
2.1. Understanding the Avalon-MM DMA Ports 2.2. Generating the Testbench 2.3. Simulating the Example Design in ModelSim* 2.4. Running a Gate-Level Simulation 2.5. Generating Synthesis Files 2.6. Compiling the Design 2.7. Creating a Quartus® Prime Project
2.2. Generating the Testbench x
2.2.1. Understanding the Simulation Generated Files 2.2.2. Understanding Simulation Log File Generation
3. Parameter Settings x
3.1. System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. PCI Express and PCI Capabilities Parameters 3.5. PCIe Address Space Settings
3.4. PCI Express and PCI Capabilities Parameters x
3.4.1. Device Capabilities 3.4.2. Error Reporting 3.4.3. Link Capabilities 3.4.4. MSI and MSI-X Capabilities 3.4.5. Power Management
4. Registers x
4.1. Correspondence between Configuration Space Registers and the PCIe Specification 4.2. Type 0 Configuration Space Registers 4.3. Type 1 Configuration Space Registers 4.4. PCI Express Capability Structures 4.5. Intel-Defined VSEC Registers 4.6. Advanced Error Reporting Capability 4.7. DMA Descriptor Controller Registers 4.8. Control Register Access (CRA) Avalon-MM Slave Port
4.5. Intel-Defined VSEC Registers x
4.5.1. CvP Registers
4.6. Advanced Error Reporting Capability x
4.6.1. Uncorrectable Internal Error Mask Register 4.6.2. Uncorrectable Internal Error Status Register 4.6.3. Correctable Internal Error Mask Register 4.6.4. Correctable Internal Error Status Register
4.7. DMA Descriptor Controller Registers x
4.7.1. Read DMA Descriptor Controller Registers 4.7.2. Write DMA Descriptor Controller Registers 4.7.3. Read DMA and Write DMA Descriptor Format 4.7.4. Read DMA Example 4.7.5. Software Program for Simultaneous Read and Write DMA
5. Error Handling x
5.1. Physical Layer Errors 5.2. Data Link Layer Errors 5.3. Transaction Layer Errors 5.4. Error Reporting and Data Poisoning 5.5. Uncorrectable and Correctable Error Status Bits
6. PCI Express Protocol Stack x
6.1. Top-Level Interfaces 6.2. Data Link Layer 6.3. Physical Layer
6.1. Top-Level Interfaces x
6.1.1. Avalon-MM DMA Interface 6.1.2. Clocks and Reset 6.1.3. Transceiver Reconfiguration 6.1.4. Interrupts 6.1.5. PIPE
7. V-Series Avalon-MM DMA for PCI Express x
7.1. Understanding the Internal DMA Descriptor Controller 7.2. Understanding the External DMA Descriptor Controller
8. Transceiver PHY IP Reconfiguration x
8.1. Connecting the Transceiver Reconfiguration Controller IP Core 8.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
C. Document Revision History x
C.1. Document Revision History for the V-Series Avalon® Memory Mapped (Avalon-MM) DMA Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Registers
5. Error Handling
6. PCI Express Protocol Stack
7. V-Series Avalon-MM DMA for PCI Express
8. Transceiver PHY IP Reconfiguration
A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe
B. V-Series Interface for PCIe Solutions User Guide Archive
C. Document Revision History

1.10. V-Series Recommended Speed Grades

Altera recommends setting the Quartus® Prime Analysis & Synthesis Settings Optimization Technique to Speed when the Application Layer clock frequency is 250 MHz. For information about optimizing synthesis, refer to Setting Up and Running Analysis and Synthesis in Quartus® Prime Help. For more information about how to effect the Optimization Technique settings, refer to Area and Timing Optimization in volume 2 of the Quartus® Prime Handbook.

Table 8.  Arria V Recommended Speed Grades for All Link Widths, Link Widths, and Application Layer Clock Frequencies

Link Rate

Link Width

Interface Width

Application Clock Frequency (MHz)

Recommended Speed Grades

Gen1

×1

64 bits

62.5 3,125

–4,–5,–6

×2

64 bits

125

–4,–5,–6

×4

64 bits

125

–4,–5,–6

×8

128 bits

125

–4,–5,–6

Gen2

×1

64 bits

125

–4,–5

×2

64 bits

125

–4,–5

×4

128 bits

125

–4,–5

Table 9.  Arria V GZ Recommended Speed Grades for All Widths, Link Widths, and Application Layer Clock Frequencies

Link Rate

Link Width

Interface Width

Application Clock Frequency (MHz)

Recommended Speed Grades

Gen1

x1

64 bits

62.5 4,125

–1, –2, –3, –4

x2

64 bits

125

–1, –2, –3, –4

x4

64 bits

125

–1, –2, –3, –4

x8

64 bits

250

–1, –2, –3 5

x8

128 Bits

125

–1, –2, –3, –4

Gen2

x1

64 bits

125

–1, –2, –3, –4

x2

64 bits

125

–1, –2, –3, –4

x4

64 bits

250

–1, –2, –3 (5)

x4

128 bits

125

–1, –2, –3, –4

x8

128 bits

250

–1, –2, –3 (5)

x8

256 bits

125

–1, –2, –3, –4

Gen3

x1

64 bits

125

–1, –2, –3, –4

x2

64 bits

250

–1, –2, –3, –4

x2

128 bits

125

–1, –2, –3, –4

x4

128 bits

250

–1, –2, –3(5)

x4

256 bits

125

–1, –2, –3,–4

x8

256 bits

250

–1, –2, –3(5)

Table 10.  Cyclone V Recommended Speed Grades for All Link Widths, Link Widths, and Application Layer Clock Frequencies The Gen2 data rate requires Cyclone V GT devices.

Link Rate

Link Width

Interface Width

Application Clock Frequency (MHz)

Recommended Speed Grades

Gen1

×1

64 bits

62.5 6,125

–6, –7,–8

×2

64 bits

125

–6, –7,–8

×4

64 bits

125

–6, –7,–8

Gen2

×1

64 bits

125

–7

×2

64 bits

125

–7

×4

128 bits

125

–7

Table 11.  Stratix V Recommended Speed Grades for All Widths, Link Widths, and Application Layer Clock Frequencies

Link Rate

Link Width

Interface Width

Application Clock Frequency (MHz)

Recommended Speed Grades

Gen1

x1

64 bits

62.5 7,125

–1, –2, –3, –4

x2

64 bits

125

–1, –2, –3, –4

x4

64 bits

125

–1, –2, –3, –4

x8

64 bits

250

–1, –2, –3 5 8

x8

128 Bits

125

–1, –2, –3, –4

Gen2

x1

64 bits

125

–1, –2, –3, –4

x2

64 bits

125

–1, –2, –3, –4

x4

64 bits

250

–1, –2, –3 5

x4

128 bits

125

–1, –2, –3, –4

x8

128 bits

250

–1, –2, –3 5

x8

256 bits

125

–1, –2, –3, –4

Gen3

x1

64 bits

125

–1, –2, –3, –4

x2

64 bits

250

–1, –2, –3, –4

x2

128 bits

125

–1, –2, –3, –4

x4

128 bits

250

–1, –2, –3 5

x4

256 bits

125

–1, –2, –3,–4

x8

256 bits

250

–1, –2, –3 5

Related Information
3 This is a power-saving mode of operation
4 This is a power-saving mode of operation
5 The -4 speed grade is also possible for this configuration; however, it requires significant effort by the end user to close timing.
6 This is a power-saving mode of operation
7 This is a power-saving mode of operation
8 The -4 speed grade is also possible for this configuration; however, it requires significant effort by the end user to close timing.
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