V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

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ID 683514
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM DMA 3. Parameter Settings 4. Registers 5. Error Handling 6. PCI Express Protocol Stack 7. V-Series Avalon-MM DMA for PCI Express 8. Transceiver PHY IP Reconfiguration A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe B. V-Series Interface for PCIe Solutions User Guide Archive C. Document Revision History
1. Datasheet x
1.1. V-Series Avalon-MM DMA Interface for PCIe* Datasheet 1.2. Features 1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces for V-Series Devices 1.4. Release Information 1.5. V-Series Device Family Support 1.6. Design Examples 1.7. Debug Features 1.8. IP Core Verification 1.9. Resource Utilization 1.10. V-Series Recommended Speed Grades 1.11. Creating a Design for PCI Express
1.8. IP Core Verification x
1.8.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM DMA x
2.1. Understanding the Avalon-MM DMA Ports 2.2. Generating the Testbench 2.3. Simulating the Example Design in ModelSim* 2.4. Running a Gate-Level Simulation 2.5. Generating Synthesis Files 2.6. Compiling the Design 2.7. Creating a Quartus® Prime Project
2.2. Generating the Testbench x
2.2.1. Understanding the Simulation Generated Files 2.2.2. Understanding Simulation Log File Generation
3. Parameter Settings x
3.1. System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. PCI Express and PCI Capabilities Parameters 3.5. PCIe Address Space Settings
3.4. PCI Express and PCI Capabilities Parameters x
3.4.1. Device Capabilities 3.4.2. Error Reporting 3.4.3. Link Capabilities 3.4.4. MSI and MSI-X Capabilities 3.4.5. Power Management
4. Registers x
4.1. Correspondence between Configuration Space Registers and the PCIe Specification 4.2. Type 0 Configuration Space Registers 4.3. Type 1 Configuration Space Registers 4.4. PCI Express Capability Structures 4.5. Intel-Defined VSEC Registers 4.6. Advanced Error Reporting Capability 4.7. DMA Descriptor Controller Registers 4.8. Control Register Access (CRA) Avalon-MM Slave Port
4.5. Intel-Defined VSEC Registers x
4.5.1. CvP Registers
4.6. Advanced Error Reporting Capability x
4.6.1. Uncorrectable Internal Error Mask Register 4.6.2. Uncorrectable Internal Error Status Register 4.6.3. Correctable Internal Error Mask Register 4.6.4. Correctable Internal Error Status Register
4.7. DMA Descriptor Controller Registers x
4.7.1. Read DMA Descriptor Controller Registers 4.7.2. Write DMA Descriptor Controller Registers 4.7.3. Read DMA and Write DMA Descriptor Format 4.7.4. Read DMA Example 4.7.5. Software Program for Simultaneous Read and Write DMA
5. Error Handling x
5.1. Physical Layer Errors 5.2. Data Link Layer Errors 5.3. Transaction Layer Errors 5.4. Error Reporting and Data Poisoning 5.5. Uncorrectable and Correctable Error Status Bits
6. PCI Express Protocol Stack x
6.1. Top-Level Interfaces 6.2. Data Link Layer 6.3. Physical Layer
6.1. Top-Level Interfaces x
6.1.1. Avalon-MM DMA Interface 6.1.2. Clocks and Reset 6.1.3. Transceiver Reconfiguration 6.1.4. Interrupts 6.1.5. PIPE
7. V-Series Avalon-MM DMA for PCI Express x
7.1. Understanding the Internal DMA Descriptor Controller 7.2. Understanding the External DMA Descriptor Controller
8. Transceiver PHY IP Reconfiguration x
8.1. Connecting the Transceiver Reconfiguration Controller IP Core 8.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
C. Document Revision History x
C.1. Document Revision History for the V-Series Avalon® Memory Mapped (Avalon-MM) DMA Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Registers
5. Error Handling
6. PCI Express Protocol Stack
7. V-Series Avalon-MM DMA for PCI Express
8. Transceiver PHY IP Reconfiguration
A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe
B. V-Series Interface for PCIe Solutions User Guide Archive
C. Document Revision History

7.2. Understanding the External DMA Descriptor Controller

Using the External DMA Descriptor Controller provides more flexibility. You can either modify or replace it to meet your system requirements.You may need to modify the DMA Descriptor Controller for the following reasons:
  • To implement multi-channel operation
  • To implement the descriptors as a linked list or to implement a custom DMA programming model
  • To store descriptors in a local memory, instead of system (host-side) memory

To interface to the DMA logic included in this variant, the custom DMA descriptor controller must implement the following functions:

  • It must communicate with the Write Mover and Read Mover to copy the descriptor table to local memory.
  • The Write Mover and Read Mover must execute the descriptors stored in local memory.
  • The DMA Avalon-MM write (WrDCM_Master) and read (RdDCM_Master) masters must be able to update status to the TX slave (TXS).
Figure 19. Avalon-MM DMA Block Diagram with External DMA Descriptor ControllerThis Platform Designer design example, ep_g3x8_avmm256.qsys, is available in the <install_dir>/ ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/a10 directory. This screen capture filters out some interface types for clarity.
Figure 20. Avalon-MM DMA Block Diagram with External DMA Descriptor ControllerThis block diagram corresponds to the Platform Designer system shown in the previous figure. When the DMA Descriptor Controller is instantiated as a external component, it drives table entries on the RdDmaRxData_i[159:0] and WrDmaRxData_i[159:0] buses.

The DMA modules shown in the block diagram implements the following functionality:

  • Read DMA (Read Mover and dma_rd_master) –Transfers data from the host domain to the local domain. It sends Memory Read TLPs upstream and writes the completion data to external Avalon-MM components using its own high performance master port. It follows the PCI Express Base Specification rules concerning tags, flow control credits, read completion boundary, maximum read size, and 4 KB boundaries.
  • Write DMA (Write Mover and dma_wr_master) – Transfers data from the local domain to the host domain. It reads data from an Avalon-MM slave component using its own high performance master port. It sends data upstream using Memory Write TLPs. It follows the PCI Express Base Specification rules concerning tags, flow control credits, RX buffer completion rules, maximum payload size, and 4 KB boundaries.
  • DMA Descriptor Controller–Manages read and write DMA operations. Host software programs its internal registers with the location of the descriptor table residing in the PCI Express system memory. The descriptor control logic directs the DMA read logic to copy the entire table to the local FIFO. It then fetches the table entries from the FIFO one at a time. It directs the appropriate DMA to transfer the data between the local and host domains. It also sends DMA status upstream via the TX slave single dword port (TXS). For more information about the DMA Descriptor Controller registers, refer to DMA Descriptor Controller Registers.
  • RX Master (PCIe BAR0-1) –Allows the host to program internal registers of the DMA Descriptor Controller.
  • TX Slave (TXS) – The DMA Descriptor Controller reports status on each read and write descriptor to this Avalon-MM slave. It also uses this port to send MSI requests.
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