V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

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ID 683514
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM DMA 3. Parameter Settings 4. Registers 5. Error Handling 6. PCI Express Protocol Stack 7. V-Series Avalon-MM DMA for PCI Express 8. Transceiver PHY IP Reconfiguration A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe B. V-Series Interface for PCIe Solutions User Guide Archive C. Document Revision History
1. Datasheet x
1.1. V-Series Avalon-MM DMA Interface for PCIe* Datasheet 1.2. Features 1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces for V-Series Devices 1.4. Release Information 1.5. V-Series Device Family Support 1.6. Design Examples 1.7. Debug Features 1.8. IP Core Verification 1.9. Resource Utilization 1.10. V-Series Recommended Speed Grades 1.11. Creating a Design for PCI Express
1.8. IP Core Verification x
1.8.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM DMA x
Avalon-MM DMA for PCI Express On-Chip Memory IP core Descriptor Controller Transceiver Reconfiguration Controller IP Core Intel PCIe Reconfig Driver IP Core Block Diagram of the Avalon-MM DMA for PCI Express Example Design Design Example Limitations 2.1. Understanding the Avalon-MM DMA Ports 2.2. Generating the Testbench 2.3. Simulating the Example Design in ModelSim* 2.4. Running a Gate-Level Simulation 2.5. Generating Synthesis Files 2.6. Compiling the Design 2.7. Creating a Quartus® Prime Project
2.2. Generating the Testbench x
2.2.1. Understanding the Simulation Generated Files 2.2.2. Understanding Simulation Log File Generation
3. Parameter Settings x
3.1. System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. PCI Express and PCI Capabilities Parameters 3.5. PCIe Address Space Settings
3.4. PCI Express and PCI Capabilities Parameters x
3.4.1. Device Capabilities 3.4.2. Error Reporting 3.4.3. Link Capabilities 3.4.4. MSI and MSI-X Capabilities 3.4.5. Power Management
4. Registers x
4.1. Correspondence between Configuration Space Registers and the PCIe Specification 4.2. Type 0 Configuration Space Registers 4.3. Type 1 Configuration Space Registers 4.4. PCI Express Capability Structures 4.5. Intel-Defined VSEC Registers 4.6. Advanced Error Reporting Capability 4.7. DMA Descriptor Controller Registers 4.8. Control Register Access (CRA) Avalon-MM Slave Port
4.5. Intel-Defined VSEC Registers x
4.5.1. CvP Registers
4.6. Advanced Error Reporting Capability x
4.6.1. Uncorrectable Internal Error Mask Register 4.6.2. Uncorrectable Internal Error Status Register 4.6.3. Correctable Internal Error Mask Register 4.6.4. Correctable Internal Error Status Register
4.7. DMA Descriptor Controller Registers x
4.7.1. Read DMA Descriptor Controller Registers 4.7.2. Write DMA Descriptor Controller Registers 4.7.3. Read DMA and Write DMA Descriptor Format 4.7.4. Read DMA Example 4.7.5. Software Program for Simultaneous Read and Write DMA
5. Error Handling x
5.1. Physical Layer Errors 5.2. Data Link Layer Errors 5.3. Transaction Layer Errors 5.4. Error Reporting and Data Poisoning 5.5. Uncorrectable and Correctable Error Status Bits
6. PCI Express Protocol Stack x
6.1. Top-Level Interfaces 6.2. Data Link Layer 6.3. Physical Layer
6.1. Top-Level Interfaces x
6.1.1. Avalon-MM DMA Interface 6.1.2. Clocks and Reset 6.1.3. Transceiver Reconfiguration 6.1.4. Interrupts 6.1.5. PIPE
7. V-Series Avalon-MM DMA for PCI Express x
7.1. Understanding the Internal DMA Descriptor Controller 7.2. Understanding the External DMA Descriptor Controller
8. Transceiver PHY IP Reconfiguration x
8.1. Connecting the Transceiver Reconfiguration Controller IP Core 8.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
C. Document Revision History x
C.1. Document Revision History for the V-Series Avalon® Memory Mapped (Avalon-MM) DMA Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Registers
5. Error Handling
6. PCI Express Protocol Stack
7. V-Series Avalon-MM DMA for PCI Express
8. Transceiver PHY IP Reconfiguration
A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe
B. V-Series Interface for PCIe Solutions User Guide Archive
C. Document Revision History

2. Getting Started with the Avalon-MM DMA

You can download the Platform Designer design example, pcie_de_ep_dma_g3x8_integrated.qsys, from the <install_dir>/ ip/altera/altera_pcie/altera_pcie_hip_256_avmm/example_design/<dev> directory.

Note: This design example provides instructions for generating simulation and synthesis files, but does not not generate all the files necessary to download the design to hardware. Refer to AN 690: PCI Express Avalon-MM DMA Reference Design and AN 708: PCI Express DMA Reference Design Using External DDR3 Memory for Stratix V and Arria V GZ Devices This reference design for reference designs that include all files necessary to download your design to an FPGA Development Kit.

The design example includes the following components:

Avalon-MM DMA for PCI Express

This IP core includes highly efficient DMA Read and DMA Write modules. The DMA Read and Write modules effectively move large blocks of data between the PCI Express address domain and the Avalon-MM address domain using burst data transfers. Depending on the configuration you select, the DMA Read and DMA Write modules use either a 128- or 256-bit Avalon-MM datapath.

In addition to high performance data transfer, the DMA Read and DMA Write modules ensure that the requests on the PCI link adhere to the PCI Express Base Specification, 3.0. The DMA Read and Write engines also perform the following functions:

  • Divide the original request into multiple requests to avoid crossing 4KByte boundaries.
  • Divide the original request into multiple requests to ensure that the maximum payload size is equal to or smaller than the maximum payload size for write requests and maximum read request size for read requests.
  • Supports out-of-order completions when the original request is divided into multiple requests to adhere to the read request size. The Read Completions can come back in any order. The Read DMA Avalon-MM master port supports out-of-order Completions by writing the Read Completions to the correct locations. The Read DMA Avalon® -MM master port does not have an internal reordering buffer.

Using the DMA Read and DMA Write modules, you can specify descriptor entry table entries with large payloads.

On-Chip Memory IP core

This IP core stores the DMA data. This memory has a 256-bit data width.

Descriptor Controller

The Descriptor Controller manages the Read DMA and Write DMA modules. Host software programs the Descriptor Controller internal registers with the location of the descriptor table. The Descriptor Controller instructs the Read DMA module to copy the entire table to its internal FIFO. It then pushes the table entries to DMA Read or DMA Write modules to transfer data. The Descriptor Controller also sends DMA status upstream via an Avalon-MM TX slave port.

In this example design the Descriptor Controller parameter, Instantiate internal descriptor controller, is on. Consequently, the Descriptor Controller is integrated into the Avalon-MM DMA bridge as shown in the figure below. Embedding the Descriptor Controller in the Avalon-MM DMA bridge simplifies the design. If you plan to replace the Descriptor Controller IP core with your own implementation, do not turn on the Instantiate internal descriptor controller in the parameter editor when parameterizing the IP core.

The Descriptor Controller supports the following features:
  • A single duplex channel.
  • Minimum transfer size of one dword (4 bytes).
  • Maximum transfer size of 1 M (1024 * 1024) - 4 bytes.
    Note: Although the Descriptor Controller supports a maximum transfer size of (1 M (1024 * 1024) - 4 bytes), the on-chip memory in this design example is smaller. Consequently, this design example cannot handle the maximum transfer size.
  • Endpoints, only.
  • Provides status to host software by generating an MSI interrupt when the DMA transfer completes.

Transceiver Reconfiguration Controller IP Core

The Transceiver Reconfiguration Controller performs offset cancellation to compensate for variations due to process, voltage, and temperature (PVT).

The following provides a high‑level block diagram of the V-Series Avalon-MM DMA for PCI Express Design Example.

Intel PCIe Reconfig Driver IP Core

The PCIe Reconfig Driver drives the Transceiver Reconfiguration Controller. This driver is a plain text Verilog HDL file that you can modify if necessary to meet your system requirements.

Block Diagram of the Avalon-MM DMA for PCI Express Example Design

Design Example Limitations

This design example is intended to show basic DMA functionality. It is not a substitute for a robust verification testbench. If you modify this testbench, be sure to verify that the modifications result in the correct behavior.


Section Content
Understanding the Avalon-MM DMA Ports
Generating the Testbench
Simulating the Example Design in ModelSim
Running a Gate-Level Simulation
Generating Synthesis Files
Compiling the Design
Creating a Quartus Prime Project

Related Information
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