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1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Registers
5. Error Handling
6. PCI Express Protocol Stack
7. V-Series Avalon-MM DMA for PCI Express
8. Transceiver PHY IP Reconfiguration
A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe
B. V-Series Interface for PCIe Solutions User Guide Archive
C. Document Revision History
1.1. V-Series Avalon-MM DMA Interface for PCIe* Datasheet
1.2. Features
1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces for V-Series Devices
1.4. Release Information
1.5. V-Series Device Family Support
1.6. Design Examples
1.7. Debug Features
1.8. IP Core Verification
1.9. Resource Utilization
1.10. V-Series Recommended Speed Grades
1.11. Creating a Design for PCI Express
4.1. Correspondence between Configuration Space Registers and the PCIe Specification
4.2. Type 0 Configuration Space Registers
4.3. Type 1 Configuration Space Registers
4.4. PCI Express Capability Structures
4.5. Intel-Defined VSEC Registers
4.6. Advanced Error Reporting Capability
4.7. DMA Descriptor Controller Registers
4.8. Control Register Access (CRA) Avalon-MM Slave Port
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coreclkout_hip can drive the Application Layer clock along with the pld_clk input to the IP core. The pld_clk can optionally be sourced by a different clock than coreclkout_hip. The pld_clk minimum frequency cannot be lower than the coreclkout_hip frequency. Based on specific Application Layer constraints, a PLL can be used to derive the desired frequency.
Note: For Gen3, Intel recommends using a common reference clock (0 ppm) because when using separate reference clocks (non 0 ppm), the PCS occasionally must insert SKP symbols, potentially causing the PCIe link to go to recovery. Gen1 or Gen2 modes are not affected by this issue. Systems using the common reference clock (0 ppm) are not affected by this issue. The primary repercussion of this issue is a slight decrease in bandwidth. On Gen3 x8 systems, this bandwidth impact is negligible. If non 0 ppm mode is required, so that separate reference clocks are used, please contact Intel for further information and guidance.