V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

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ID 683514
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM DMA 3. Parameter Settings 4. Registers 5. Error Handling 6. PCI Express Protocol Stack 7. V-Series Avalon-MM DMA for PCI Express 8. Transceiver PHY IP Reconfiguration A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe B. V-Series Interface for PCIe Solutions User Guide Archive C. Document Revision History
1. Datasheet x
1.1. V-Series Avalon-MM DMA Interface for PCIe* Datasheet 1.2. Features 1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces for V-Series Devices 1.4. Release Information 1.5. V-Series Device Family Support 1.6. Design Examples 1.7. Debug Features 1.8. IP Core Verification 1.9. Resource Utilization 1.10. V-Series Recommended Speed Grades 1.11. Creating a Design for PCI Express
1.8. IP Core Verification x
1.8.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM DMA x
2.1. Understanding the Avalon-MM DMA Ports 2.2. Generating the Testbench 2.3. Simulating the Example Design in ModelSim* 2.4. Running a Gate-Level Simulation 2.5. Generating Synthesis Files 2.6. Compiling the Design 2.7. Creating a Quartus® Prime Project
2.2. Generating the Testbench x
2.2.1. Understanding the Simulation Generated Files 2.2.2. Understanding Simulation Log File Generation
3. Parameter Settings x
3.1. System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. PCI Express and PCI Capabilities Parameters 3.5. PCIe Address Space Settings
3.4. PCI Express and PCI Capabilities Parameters x
3.4.1. Device Capabilities 3.4.2. Error Reporting 3.4.3. Link Capabilities 3.4.4. MSI and MSI-X Capabilities 3.4.5. Power Management
4. Registers x
4.1. Correspondence between Configuration Space Registers and the PCIe Specification 4.2. Type 0 Configuration Space Registers 4.3. Type 1 Configuration Space Registers 4.4. PCI Express Capability Structures 4.5. Intel-Defined VSEC Registers 4.6. Advanced Error Reporting Capability 4.7. DMA Descriptor Controller Registers 4.8. Control Register Access (CRA) Avalon-MM Slave Port
4.5. Intel-Defined VSEC Registers x
4.5.1. CvP Registers
4.6. Advanced Error Reporting Capability x
4.6.1. Uncorrectable Internal Error Mask Register 4.6.2. Uncorrectable Internal Error Status Register 4.6.3. Correctable Internal Error Mask Register 4.6.4. Correctable Internal Error Status Register
4.7. DMA Descriptor Controller Registers x
4.7.1. Read DMA Descriptor Controller Registers 4.7.2. Write DMA Descriptor Controller Registers 4.7.3. Read DMA and Write DMA Descriptor Format 4.7.4. Read DMA Example 4.7.5. Software Program for Simultaneous Read and Write DMA
5. Error Handling x
5.1. Physical Layer Errors 5.2. Data Link Layer Errors 5.3. Transaction Layer Errors 5.4. Error Reporting and Data Poisoning 5.5. Uncorrectable and Correctable Error Status Bits
6. PCI Express Protocol Stack x
6.1. Top-Level Interfaces 6.2. Data Link Layer 6.3. Physical Layer
6.1. Top-Level Interfaces x
6.1.1. Avalon-MM DMA Interface 6.1.2. Clocks and Reset 6.1.3. Transceiver Reconfiguration 6.1.4. Interrupts 6.1.5. PIPE
7. V-Series Avalon-MM DMA for PCI Express x
7.1. Understanding the Internal DMA Descriptor Controller 7.2. Understanding the External DMA Descriptor Controller
8. Transceiver PHY IP Reconfiguration x
8.1. Connecting the Transceiver Reconfiguration Controller IP Core 8.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
C. Document Revision History x
C.1. Document Revision History for the V-Series Avalon® Memory Mapped (Avalon-MM) DMA Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Registers
5. Error Handling
6. PCI Express Protocol Stack
7. V-Series Avalon-MM DMA for PCI Express
8. Transceiver PHY IP Reconfiguration
A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe
B. V-Series Interface for PCIe Solutions User Guide Archive
C. Document Revision History

The RX Master module translates read and write TLPs received from the PCIe link to Avalon-MM requests for Platform Designer components connected to the interconnect. This module allows other PCIe components, including host software, to access other Avalon-MM slaves connected in the Platform Designer system.

If burst mode is not enabled, the RX Master module only supports 32-bit read or write request. All other requests received from the PCIe link are considered a violation of this device’s programming model, and are therefore handled with the PCIe Completer Abort status. You can enable burst mode for BAR2 using 32-bit addressing or BAR2 and BAR3 using 64-bit addressing. When enabled, the module supports dword, burst read, or write requests. When the Descriptor Controller is internally instantiated, the RX Master for BAR0 is used internally and not available for other uses.

Note: When you enable burst mode for BAR2, Flush reads (i.e. reads with all byte enables set to 0) are not supported.
RX Master Control Interface Ports for BAR Access Each BAR has one corresponding RX Master Control interface. In this table, <n> is the BAR number.

Signal Name

Direction

Description

RxmRead_<n>_o

Output

When asserted, indicates an Avalon-MM read request.

RxmWrite_<n>_o

Output

When asserted, indicates an Avalon-MM write request.

RxmAddress_<n>_o[<w>-1:0]

Output

Specifies the Avalon-MM byte address. Because all addresses are byte addresses, the meaningful bits of this address are [<w>-1:2]. Bits 1 and 0 have a value of 0. <w> can be 32 or 64.

RxmBurstCount_<n>_o[5:0]

Output

Specifies the burst count in dwords (32 bits). This optional signal is available for BAR2 when you turn on Enable burst capabilities for RXM BAR2 ports.

RxmByteEnable_<n>_o[<w>-1:0]

Output

Specifies the valid bytes of data to be written. <w> has the following values:

  • 4: for the non-bursting RX Master
  • 32: for the bursting 128-bit Avalon-MM interface
  • 64: for the bursting 256-bit Avalon-MM interface
RxmDataWrite_<n>_o[<w>-1:0]

Output

Specifies the Avalon-MM write data. <w> has the following values:

  • 32: for the non-bursting RX Master
  • 128: for the bursting 128-bit Avalon-MM interface
  • 256: for the bursting 256-bit Avalon-MM interface
RxmReadData_<n>_i[<w>-1:0]

Input

Specifies the Avalon-MM read data. <w> has the following values:

  • 32: for the non-bursting RX Master
  • 128: for the bursting 128-bit Avalon-MM interface
  • 256: for the bursting 256-bit Avalon-MM interface
RxmReadDataValid_ <n> _i[31:0]

Input

When asserted, indicates that RxmReadData_i[31:0]is valid.
RxmWaitRequest_<n>_i

Input

When asserted indicates that the control register access Avalon-MM slave port is not ready to respond.

RXM Master Writes to Memory in the Avalon-MM Address Space
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