Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683505
Date 1/27/2021
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling the Compilation-Only Project 1.7. Compiling and Configuring the Design Example in Hardware 1.8. Testing the Hardware Design Example
1.8. Testing the Hardware Design Example x
1.8.1. Testing the Hardware Design Example using Ethernet Link Inspector 1.8.2. Testing the Hardware Design Example using Ethernet Toolkit
2. Design Example Description x
2.1. Features 2.2. Design Example Behavior 2.3. Design Example Interface Signals 2.4. Design Example Registers
2.4. Design Example Registers x
2.4.1. Packet Generator Programming Sequence
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

1.8. Testing the Hardware Design Example

After you compile the Low Latency 100G Ethernet Intel Stratix 10 FPGA core design example and configure it on your Intel® Stratix® 10 device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.

To turn on the System Console and test the hardware design example, follow these steps:

  1. After the hardware design example is configured on the Intel® Stratix® 10 device, in the Intel® Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
  2. In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
  3. Type source main.tcl to open a connection to the JTAG master.

You can program the IP core with the following design example commands:

  • chkphy_status: Displays the clock frequencies and PHY lock status.
  • chkmac_stats: Displays the values in the MAC statistics counters.
  • clear_all_stats: Clears the IP core statistics counters.
  • start_pkt_gen: Starts the packet generator.
  • stop_pkt_gen: Stops the packet generator.
  • loop_on: Turns on internal serial loopback
  • loop_off: Turns off internal serial loopback.
  • reg_read <addr>: Returns the IP core register value at <addr>.
  • reg_write <addr> <data>: Writes <data> to the IP core register at address <addr>.
The successful test run displays output confirming the following behavior:
  1. Turning off packet generation
  2. Enabling loopback
  3. Waiting for RX clock to settle
  4. Printing PHY status
  5. Clearing MAC statistics counters
  6. Sending packets
  7. Reading MAC statistics counters
  8. Printing MAC statistics counters, which show 0 in all error counters

The following sample output illustrates a successful test run:


--- Turning off packet generation ---- 
--------------------------------------

--------- Enabling loopback ----------
--------------------------------------

--- Wait for RX clock to settle... ---
--------------------------------------

-------- Printing PHY status ---------
--------------------------------------

 RX PHY Register Access: Checking Clock Frequencies (KHz)

          REFCLK                :0 (KHZ)
          TXCLK                 :39063   (KHZ)
          RXCLK                 :39064   (KHZ)
          RX RECOV CLK          :31250   (KHZ)
          TX-IO CLOCK           :31251   (KHZ)
 RX PHY Status Polling

 Rx Frequency Lock Status       0x0000000f

 Mac Clock in OK Condition?     0x00000007

 Rx Frame Error                 0x00000000

 Rx PHY Fullly Aligned?         0x00000001

 Rx AM LOCK Condition?          0x00000001

 Rx Lanes Deskewed Condition?   0x00000001

---- Clearing MAC stats counters -----
--------------------------------------

--------- Sending packets... ---------
--------------------------------------

----- Reading MAC stats counters -----
--------------------------------------


 ======================================================================
                        STATISTICS FOR BASE 0x0900 (Rx)
 ======================================================================
Fragmented Frames                : 0
Jabbered Frames                  : 0
Any Size with FCS Err Frame      : 0
Right Size with FCS Err Fra      : 0
Multicast data Err Frames        : 0
Broadcast data Err Frames        : 0
Unicast data Err  Frames         : 0
Multicast control  Err Frame     : 0
Broadcast control Err  Frame     : 0
Unicast control Err Frames       : 0
Pause control Err Frames         : 0
64 Byte Frames                   : 8971
65 - 127 Byte Frames             : 7995
128 - 255 Byte Frames            : 15074
256 - 511 Byte Frames            : 28808
512 - 1023 Byte Frames           : 57749
1024 - 1518 Byte Frames          : 55550
1519 - MAX Byte Frames           : 1664270
> MAX Byte Frames                : 0
Rx Frame Starts                  : 0
Multicast data OK  Frame         : 0
Broadcast data OK  Frame         : 0
Unicast data OK  Frames          : 1838417
Multicast Control Frames         : 0
Broadcast Control Frames         : 0
Unicast Control Frames           : 415
Pause Control Frames             : 0
Payload Octets OK                : 12416446222
Frame Octets OK                  : 12449532850
 ======================================================================
                        STATISTICS FOR BASE 0x0800 (Tx)
 ======================================================================
Fragmented Frames                : 0
Jabbered Frames                  : 0
Any Size with FCS Err Frame      : 0
Right Size with FCS Err Fra      : 0
Multicast data Err Frames        : 0
Broadcast data Err Frames        : 0
Unicast data Err Frames          : 0
Multicast control  Err Frame     : 0
Broadcast control Err  Frame     : 0
Unicast control Err Frames       : 0
Pause control Err Frames         : 0
64 Byte Frames                   : 8971
65 - 127 Byte Frames             : 7995
128 - 255 Byte Frames            : 15074
256 - 511 Byte Frames            : 28808
512 - 1023 Byte Frames           : 57749
1024 - 1518 Byte Frames          : 55550
1519 - MAX Byte Frames           : 1664270
> MAX Byte Frames                : 0
Tx Frame Starts                  : 0
Multicast data OK  Frame         : 0
Broadcast data OK  Frame         : 0
Unicast data OK  Frames          : 1838417
Multicast Control Frames         : 0
Broadcast Control Frames         : 0
Unicast Control Frames           : 0
Pause Control Frames             : 0
Payload Octets OK                : 12416446222
Frame Octets OK                  : 12449532850
---------------- Done ----------------

Section Content
Testing the Hardware Design Example using Ethernet Link Inspector
Testing the Hardware Design Example using Ethernet Toolkit

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