Figure 6. Example Design Tab in the Low Latency 100G Ethernet Intel Stratix 10 FPGA Parameter Editor

Follow these steps to generate the Low Latency 100G Ethernet Intel Stratix 10 FPGA hardware design example and testbench:

1. If you do not already have an Intel® Quartus® Prime Pro Edition project in which to integrate your Low Latency 100G Ethernet Intel Stratix 10 FPGA core, you must create one.
   1. In the Intel® Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Intel® Quartus® Prime project. The wizard prompts you to specify a device.
   2. Specify the device family Intel Stratix 10 and select a device that meets all of these requirements:
      • Transceiver tile is L-tile or H-tile (any transceiver tile)
      • Transceiver speed grade is –1 or –2
      • Core speed grade is –1 or –2
      • Production version devices
   3. Click Finish.
2. In the IP Catalog, locate and select Low Latency 100G Ethernet. The New IP Variation window appears.
3. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
4. Click OK. The parameter editor appears.
5. On the IP tab, specify the parameters for your IP core variation.
   Note: Enable RX/TX statistics counters parameter is enabled by default.
6. On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the compilation-only and hardware design examples.
   Note: You must select at least one of the Simulation and Synthesis options to generate the design example.
7. On the Example Design tab, under Generated HDL Format, only Verilog HDL is available. This IP core does not support VHDL.
8. Under Target Development Kit select the Stratix 10 GX Transceiver Signal Integrity Development Kit (Production), Stratix 10 GX Transceiver Signal Integrity Development Kit (ES), or None.
   Note: When you select Stratix 10 GX Transceiver Signal Integrity Development Kit (Production) or Stratix 10 GX Transceiver Signal Integrity Development Kit (ES) as the Target Development Kit, the design example is generated based on a specific device and it overwrites the device you selected in your project file. If you select None as the Target Development Kit, ensure the device you selected is the correct device and make changes to the pins assignment in the.qsf file. By default, the .qsf file is generated based on the device used in Stratix 10 GX Transceiver Signal Integrity Development Kit.
9. Click the Generate Example Design button. The Select Example Design Directory window appears.
10. If you want to modify the design example directory path or name from the defaults displayed (alt_e100s10_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).