Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683505
Date 1/27/2021
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling the Compilation-Only Project 1.7. Compiling and Configuring the Design Example in Hardware 1.8. Testing the Hardware Design Example
1.8. Testing the Hardware Design Example x
1.8.1. Testing the Hardware Design Example using Ethernet Link Inspector 1.8.2. Testing the Hardware Design Example using Ethernet Toolkit
2. Design Example Description x
2.1. Features 2.2. Design Example Behavior 2.3. Design Example Interface Signals 2.4. Design Example Registers
2.4. Design Example Registers x
2.4.1. Packet Generator Programming Sequence In Random Mode: In Fixed/Incremental Mode—with fixed number of packets: In Fixed/Incremental Mode— without fixed number of packets:
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

2.4.1. Packet Generator Programming Sequence

You can initiate the packet transmission from the packet generator to the IP core by programming Packet Size Configure, Packet Number Control, and PKT_GEN_TX_CTRL registers.

The programming sequence varies based on a selected mode PKT_GEN_TX_CTRL[5:4]:

In Random Mode:

  1. Set Packet Number Control[31] to 0.
  2. Set PKT_GEN_TX_CTRL[1] to 0 to start the packet transmission through the packet generator.
  3. Set PKT_GEN_TX_CTRL[1] to 1 to stop the packet generator.

In Fixed/Incremental Mode—with fixed number of packets:

  1. Configure Packet Size Configure.
  2. Configure the number of packets: Bit [31] must be set to specify Packet Number Control[30:0]
  3. Set PKT_GEN_TX_CTRL[1] to 0 to start the packet transmission through the packet generator.
  4. The packet generator stops when the number of packets reaches 0.

In Fixed/Incremental Mode— without fixed number of packets:

  1. Configure Packet Size Configure.
  2. Set Packet Number Control[31] to 0.
  3. Set PKT_GEN_TX_CTRL[1] to 0 to start the packet transmission through the packet generator.
  4. Set PKT_GEN_TX_CTRL[1] to 1 to stop the packet generator.
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