R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.1. Overview

R-Tile can be configured in one of three primary modes of operation:
  • PCIe Hard IP mode: This mode includes support for (up to Gen5) Endpoint (EP), Root Port (RP) or TLP Bypass (16 lanes maximum). When configured in this mode, R-Tile includes a complete protocol stack, including the Transaction, Data Link and Physical Layers.
  • PIPE Direct (protocol controller bypass) for FPGA user custom application needs. In this mode, both the PCIe and CXL controller stacks are entirely bypassed, and the PIPE SerDes mode interface is exported across the Embedded Multi-die Interconnect Bridge (EMIB) to the FPGA fabric. This mode allows you to implement your own custom controllers in soft IP.
  • Compute Express Link (CXL).
    Note:

    For more details on the Intel Agilex® 7 R-Tile Compute Express Link 1.1 Intel FPGA IP and the corresponding design examples, refer to:

    • Intel Agilex® 7 R-Tile Compute Express Link 1.1 Intel FPGA IP User Guide. This document is available in the Intel Resource and Documentation Center (RDC). You can download a copy or ask your local Intel Field Applications engineer to download one using the asset number 763328.
    • Intel Agilex® 7 R-Tile Compute Express Link 1.1 Intel FPGA IP Design Example User Guide. This document is available in the Intel Resource and Documentation Center (RDC). The asset number is 763513.
Figure 1. R-Tile Top-Level Block Diagram