Quick Start Guide for Intel® FPGA Development Tools on the Microsoft* Azure* Platform

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ID 683498
Date 12/22/2017
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide for Intel® FPGA Development Tools on the Microsoft* Azure* Platform 2. Document Revision History for Quick Start Guide for Intel® FPGA Development Tools on the Azure* Cloud
1. Quick Start Guide for Intel® FPGA Development Tools on the Microsoft* Azure* Platform x
1.1. Creating an Azure* Account 1.2. Licensing Intel® FPGA Software for the Azure* Cloud 1.3. Licensing IP Cores 1.4. Managing Intel® FPGA Software on the Azure* Cloud 1.5. Persistent Storage and Data Transference 1.6. Hosting a License Server in the Microsoft* Azure* Cloud 1.7. Connecting to the License Server 1.8. Example: Running Intel® Quartus® Prime Design Space Explorer II 1.9. Example: Running the ''Hello World'' Program Using the Intel® FPGA SDK for OpenCL™
1.4. Managing Intel® FPGA Software on the Azure* Cloud x
1.4.1. Signing In the Azure* Web Portal 1.4.2. Selecting Intel® FPGA Tool from the Azure* Marketplace 1.4.3. Specifying the Virtual Machine Characteristics 1.4.4. Launching the Virtual Machine 1.4.5. Connecting to the Azure* Virtual Machine Using SSH 1.4.6. Obtaining a GUI Desktop on the Running Azure* Virtual Machine 1.4.7. Opening the Intel® Quartus® Prime Software 1.4.8. Terminating the Virtual Machine
1.4.3. Specifying the Virtual Machine Characteristics x
1.4.3.1. Basic Settings 1.4.3.2. Machine Size and Instance Type 1.4.3.3. Network Settings
1.4.5. Connecting to the Azure* Virtual Machine Using SSH x
1.4.5.1. Connecting from a Windows* Computer 1.4.5.2. Connecting from a Linux Computer
1.6. Hosting a License Server in the Microsoft* Azure* Cloud x
1.6.1. Create a License Server Machine in the Azure* Cloud 1.6.2. Upload the Flexlm License Server to the Server Machine 1.6.3. Configure and Start the License Server 1.6.4. Manage the License Server
1.7. Connecting to the License Server x
1.7.1. Preserving the MAC Address
1.8. Example: Running Intel® Quartus® Prime Design Space Explorer II x
1.8.1. Starting Intel® Quartus® Prime Design Space Explorer II 1.8.2. Setting Up an Intel® Quartus® Prime Project
1. Quick Start Guide for Intel® FPGA Development Tools on the Microsoft* Azure* Platform
2. Document Revision History for Quick Start Guide for Intel® FPGA Development Tools on the Azure* Cloud

1.8.2. Setting Up an Intel® Quartus® Prime Project

Prepare your project for compilation.
  1. On the Project tab, click Open Project, and select an Intel® Quartus® Prime project.
    If you do not have an example at hand, copy an example from the $QUARTUS_ROOTDIR/qdesigns directory in your local folder.
  2. Click the Setup tab. In Compilation Type, select Local.
    Figure 14. Setup Tab
  3. On the Exploration tab, click to display Exploration Points. Specify the following settings:
    Table 7.  Settings for Exploration Points in Design Space Explorer II
    Parameter Value
    Explore Select Design Exploration.
    Skip base exploration point Enable to avoid performing a base compile with no seed or assignment changes.
    Exploration Mode Select Seed Sweep Only.
    Seeds Select Specify, and specify a range of seeds to test out.
    Figure 15. Exploration Points in Exploration Tab
  4. To configure parallelism, click Advanced. Specify the following settings:
    Table 8.  Advanced Settings for Design Space Explorer II
    Parameter Value
    Maximum parallel compilations In the example with Intel® Arria® 10 and instance type Standard_E64_V3 , enter 10.
    Maximum number of CPUs

    Number of CPUs each compiler must use.

    Since 10 compilers share the CPUs, divide the number of CPU cores by the number of compilers.

    The Standard_E64_V3 machine has 64 cores and 512 GB of physical RAM, so for the Intel® Arria® 10 example you use 6 CPUs per compiler.

    Figure 16. Advanced Settings in Exploration Tab

    On warning about performing more than one compilation simultaneously, click OK.

    Your project is ready for compilation.

  5. To compile, click Start.
    Figure 17. Start Compilation
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