Generic Flash Programmer User Guide: Intel® Quartus® Prime Pro Edition

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ID 683495
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Generic Flash Programmer User Guide Intel® Quartus® Prime Pro Edition
1. Generic Flash Programmer User Guide Intel® Quartus® Prime Pro Edition x
1.1. Supported Devices and Configuration Methods 1.2. Quad SPI Flash Byte-Addressing 1.3. Generic Flash Programmer Operation 1.4. Generic Flash Programmer Flow Templates ( Intel® Stratix® 10 devices) 1.5. Generic Flash Programmer Flow Templates ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) 1.6. Generic Flash Programmer Settings Reference 1.7. Generic Flash Programmer User Guide Revision History 1.8. Generic Flash Programmer Document Archive
1.3. Generic Flash Programmer Operation x
1.3.1. Generic Flash Programming (Programming File Generator) 1.3.2. Generic Flash Programming (Convert Programming File Dialog Box)
1.3.1. Generic Flash Programming (Programming File Generator) x
1.3.1.1. Step 1: Generate Primary Device Programming File 1.3.1.2. Step 2: Generate Secondary Programming Files (Programming File Generator) 1.3.1.3. Step 3: Program the Flash Memory Device
1.3.1.2. Step 2: Generate Secondary Programming Files (Programming File Generator) x
1.3.1.2.1. Enabling Bitstream Authentication (Programming File Generator) 1.3.1.2.2. Enabling Bitstream Encryption (Programming File Generator) 1.3.1.2.3. Defining a New Flash Memory Configuration Device
1.3.1.2.1. Enabling Bitstream Authentication (Programming File Generator) x
1.3.1.2.1.1. Specifying Additional Physical Security Settings (Programming File Generator)
1.3.2. Generic Flash Programming (Convert Programming File Dialog Box) x
1.3.2.1. Step 1: Generate Primary Device Programming Files 1.3.2.2. Step 2: Generate Secondary Programming Files (Convert Programming Files) 1.3.2.3. Step 3: Program the Flash Memory Device 1.3.2.4. Full Erase of Flash Memory Sectors
1.3.2.2. Step 2: Generate Secondary Programming Files (Convert Programming Files) x
1.3.2.2.1. Enabling Bitstream Encryption or Compression for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.3.2.2.2. Defining a New Flash Memory Device 1.3.2.2.3. Modifying Programming Flows
1.4. Generic Flash Programmer Flow Templates ( Intel® Stratix® 10 devices) x
1.4.1. Initialization Flow Template ( Intel® Stratix® 10 Devices) 1.4.2. Program Flow Template ( Intel® Stratix® 10 Devices) 1.4.3. Erase Flow Template ( Intel® Stratix® 10 Devices) 1.4.4. Verify/Blank-Check/Examine Flow Template ( Intel® Stratix® 10 Devices) 1.4.5. Termination Flow Template ( Intel® Stratix® 10 Devices)
1.5. Generic Flash Programmer Flow Templates ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) x
1.5.1. Initialization Flow Templates ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) 1.5.2. Program Flow Template ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) 1.5.3. Erase Flow Template ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) 1.5.4. Verify/Blank-Check/Examine Flow Template ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) 1.5.5. Termination Flow Template ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) 1.5.6. Programming Flow Action Properties
1.6. Generic Flash Programmer Settings Reference x
1.6.1. Device and Pin Options 1.6.2. More Security Options Dialog Box 1.6.3. Input Files Tab Settings (Programming File Generator) 1.6.4. Output Files Tab Settings (Programming File Generator) 1.6.5. Add Partition Dialog Box (Programming File Generator) 1.6.6. Bitstream Co-Signing Security Settings (Programming File Generator) 1.6.7. Convert Programming File Dialog Box 1.6.8. Compression and Encryption Settings (Convert Programming File) 1.6.9. SOF Data Properties Dialog Box (Convert Programming File) 1.6.10. Select Devices (Flash Loader) Dialog Box
1. Generic Flash Programmer User Guide Intel® Quartus® Prime Pro Edition

1.3.1.2.1.1. Specifying Additional Physical Security Settings (Programming File Generator)

Intel® Stratix® 10 devices can store security and other configuration settings in eFuses. You can enable additional physical security settings in eFuses to extend the level of device security protection.

To specify additional physical device security settings, follow these steps:

  1. Click Assignments > Device > Device and Pin Options > Security.
  2. On the Security tab, specify the First Level Signature Chain .qky file that contains the root key and one or more design signing keys for the Quartus key file setting.
  3. Click the More Options button and specify any of the following:
    Figure 10. More Security Options Dialog Box
    Table 3.  More Security Options Dialog Box Settings
    Option Description Values
    Disable JTAG Disables JTAG command and configuration of the device. Setting this eliminates JTAG as mode of attack, but also eliminates boundary scan functionality.
    • Off—inactive
    • On—active until wipe of containing design
    • On sticky—active until next POR
    • On check—checks for corresponding blown fuse
    Force SDM clock to internal oscillator Disables an external clock source for the SDM. The SDM must use the internal oscillator. Using an internal oscillator is more secure than allowing an external clock source for configuration.
    Force encryption key update Specifies that the encryption key must update by the frequency that you specify for the Encryption update ratio option. The default ration value is 31:1. Encryption supports up to 20 intermediate keys.
    Disable virtual eFuses Disables the eFuse virtual programming capability.
    Lock security eFuses Causes eFuse failure if the eFuse CRC does not match the calculated value.
    Disable HPS debug Disables debugging through the JTAG interface to access the HPS.
    Disable encryption key in eFuses Specifies that the device cannot use an AES key stored in eFuses. Rather, you can provide an extra level of security by storing the AES key in BBRAM.
    Disable encryption key in BBRAM Specifies that the device cannot use AES key stored in BBRAM. Rather, you can provide an extra level of security when you store the AES key in eFuses.
  4. Click OK.
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