Generic Flash Programmer User Guide: Intel® Quartus® Prime Pro Edition

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ID 683495
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Generic Flash Programmer User Guide Intel® Quartus® Prime Pro Edition
1. Generic Flash Programmer User Guide Intel® Quartus® Prime Pro Edition x
1.1. Supported Devices and Configuration Methods 1.2. Quad SPI Flash Byte-Addressing 1.3. Generic Flash Programmer Operation 1.4. Generic Flash Programmer Flow Templates ( Intel® Stratix® 10 devices) 1.5. Generic Flash Programmer Flow Templates ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) 1.6. Generic Flash Programmer Settings Reference 1.7. Generic Flash Programmer User Guide Revision History 1.8. Generic Flash Programmer Document Archive
1.3. Generic Flash Programmer Operation x
1.3.1. Generic Flash Programming (Programming File Generator) 1.3.2. Generic Flash Programming (Convert Programming File Dialog Box)
1.3.1. Generic Flash Programming (Programming File Generator) x
1.3.1.1. Step 1: Generate Primary Device Programming File 1.3.1.2. Step 2: Generate Secondary Programming Files (Programming File Generator) 1.3.1.3. Step 3: Program the Flash Memory Device
1.3.1.2. Step 2: Generate Secondary Programming Files (Programming File Generator) x
1.3.1.2.1. Enabling Bitstream Authentication (Programming File Generator) 1.3.1.2.2. Enabling Bitstream Encryption (Programming File Generator) 1.3.1.2.3. Defining a New Flash Memory Configuration Device
1.3.1.2.1. Enabling Bitstream Authentication (Programming File Generator) x
1.3.1.2.1.1. Specifying Additional Physical Security Settings (Programming File Generator)
1.3.2. Generic Flash Programming (Convert Programming File Dialog Box) x
1.3.2.1. Step 1: Generate Primary Device Programming Files 1.3.2.2. Step 2: Generate Secondary Programming Files (Convert Programming Files) 1.3.2.3. Step 3: Program the Flash Memory Device 1.3.2.4. Full Erase of Flash Memory Sectors
1.3.2.2. Step 2: Generate Secondary Programming Files (Convert Programming Files) x
1.3.2.2.1. Enabling Bitstream Encryption or Compression for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.3.2.2.2. Defining a New Flash Memory Device 1.3.2.2.3. Modifying Programming Flows
1.4. Generic Flash Programmer Flow Templates ( Intel® Stratix® 10 devices) x
1.4.1. Initialization Flow Template ( Intel® Stratix® 10 Devices) 1.4.2. Program Flow Template ( Intel® Stratix® 10 Devices) 1.4.3. Erase Flow Template ( Intel® Stratix® 10 Devices) 1.4.4. Verify/Blank-Check/Examine Flow Template ( Intel® Stratix® 10 Devices) 1.4.5. Termination Flow Template ( Intel® Stratix® 10 Devices)
1.5. Generic Flash Programmer Flow Templates ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) x
1.5.1. Initialization Flow Templates ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) 1.5.2. Program Flow Template ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) 1.5.3. Erase Flow Template ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) 1.5.4. Verify/Blank-Check/Examine Flow Template ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) 1.5.5. Termination Flow Template ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) 1.5.6. Programming Flow Action Properties
1.6. Generic Flash Programmer Settings Reference x
1.6.1. Device and Pin Options General Device Options Configuration Options Configuration PIN Dialog Box 1.6.2. More Security Options Dialog Box 1.6.3. Input Files Tab Settings (Programming File Generator) 1.6.4. Output Files Tab Settings (Programming File Generator) 1.6.5. Add Partition Dialog Box (Programming File Generator) 1.6.6. Bitstream Co-Signing Security Settings (Programming File Generator) 1.6.7. Convert Programming File Dialog Box 1.6.8. Compression and Encryption Settings (Convert Programming File) 1.6.9. SOF Data Properties Dialog Box (Convert Programming File) 1.6.10. Select Devices (Flash Loader) Dialog Box
1. Generic Flash Programmer User Guide Intel® Quartus® Prime Pro Edition

1.6.1. Device and Pin Options

The following tables describe Device & Pin Option settings that impact Generic Flash Programmer. To access, click Assignments > Device > Device & Pin Options.

General Device Options

Allow you to specify basic device configuration options that are independent of a specific configuration scheme. To access these settings, click Assignments > Device > Device and Pin Options > General.

Table 12.  General Device Options
Option Description
Options
Note: Not supported for Intel® Stratix® 10 devices.
  • Auto-restart configuration after error—restarts the configuration process automatically if a data error is encountered. If this option is turned off, you must externally direct the device to restart the configuration process if an error occurs. This option is available for passive serial and active serial configuration schemes.
  • Release clears before tri-states—releases the clear signal on registered logic cells and I/O cells before releasing the output enable override on tri-state buffers. If this option is turned off, the output enable signals are released before the clear overrides are released.
  • Enable user-supplied start-up clock (CLKUSR)—uses a user-supplied clock on the CLKUSR pin for initialization. When turned off, external circuitry is required to provide the initialization clock on the DCLK pin in the Passive Serial and Passive Parallel Synchronous configuration schemes; in the Passive Parallel Asynchronous configuration scheme, the device uses an internal initialization clock.
  • Enable device-wide reset (DEV_CLRn)—enables the DEV_CLRn pin, which allows all registers of the device to be reset by an external source. If this option is turned off, the DEV_CLRn pin is disabled when the device operates in user mode and is available as a user I/O pin.
  • Enable device-wide output enable (DEV_OE)—enables the DEV_OE pin when the device is in user mode. If this option is turned on, all outputs on the chip operate normally. When the pin is disabled, all outputs are tri-stated. If this option is turned off, the DEV_OE pin is disabled when the device operates in user mode and is available as a user I/O pin.
  • Enable INIT_DONE output—enables the INIT_DONE pin, which allows you to externally monitor when initialization is complete and the device is in user mode. If this option is turned off, the INIT_DONE pin is disabled when the device operates in user mode and is available as a user I/O pin.
  • Enable JTAG Pin Sharing—enables the JTAG pin sharing feature. The JTAGEN pin is enables and becomes a dedicated input pin in user mode. JTAG pins (TDO, TCK, TDI, and TMS pins) are available as test pins when the JTAGEN pin is pull low. JTAG pins are dedicated when the JTAGEN pin is high. If this option is turned off, the JTAGEN pin is disabled when the device operates in user mode and is available as a user I/O pin. JTAG pins are retained as dedicated JTAG pins.
  • Enable nCONFIG, nStatus, and CONF_DONE pins—enables the major configuration pins, nCONFIG, nSTATUS, and CONF_DONE pin in user mode. If this option is turned off, the nCONFIG, nSTATUS, and CONF_DONE pins are disabled when the device operates in user mode and are available as user I/O pins.
  • Enable OCT_DONE —enables the OCT_DONE pin, which controls whether the INIT_DONE pin is gated by OCT_DONE pin. If this option is turned off, the INIT_DONE pin is not gated by the OCT_DONE pin.
  • Enable security bit support—enables the security bit support, which prevents data in a device from being obtained and used to program another device. This option is available for supported device ( MAX® II, and MAX® V) families.
  • Set unused TDS pins to GND—sets the unused temperature sensing diode TSD pins, TEMPDIODEp and TEMPDIODEn to GND in the pin. By default, TSD pins are available for connection to an external temperature sensing device; however, you must manually connect the pins to GND if they are not connected. When turned on, this option updates the information in the .pin file and does not affect FPGA behavior.
  • Enable CONFIG_SEL pin—enables the BOOT_SEL pin in user mode. If this option is turned off, the BOOT_SEL pin is disabled when the device operates in user mode and is available as a user I/O pin.
  • Enable nCEO pin—enables the nCEO pin. This pin should be connected to the nCE of the succeeding device when multiple devices are being programmed. If this option is turned off, the nCEO pin is disabled when the device operates in user mode and is available as a user I/O pin.
  • Enable autonomous PCIe HIP mode—releases the PCIe HIP after periphery configuration, before device core configuration completes. This option only takes effect if CvP mode is disabled.
  • Enable the HPS early release of HPS IO—releases the HPS shared I/O bank after the IOCSR programming.
Auto usercode Sets the JTAG user code to match the checksum value of the device programming file. The programming file is a .pof for non-volatile devices, or an .sof for SRAM-based devices. If you turn on this option, the JTAG user code option is not available.
JTAG user code Specifies a hexadecimal number for the device selected for the current Compiler settings. The JTAG user code is an extension of the option register. This data can be read with the JTAG USERCODE instruction. If you turn on Auto usercode, this option is not available.
In-system programming clamp state Allows you to specify the state that the pins take during in-system programming for used pins that do not have an in-system programming clamp state assignment. Unused pins and dedicated inputs must always be tri-stated for in-system programming. Used pins are tri-stated by default during in-system programming, which electrically isolates the device from other devices on the board. At times, however, in order to prevent system damage you may want to specify the logic level for used pins during in-system programming. The following settings are available:
  • Tri-state—the pins are tri-stated.
  • High—the pins drive VCCIO.
  • Low—the pins drive GND.
  • Sample and Sustain—the pins drive the level captured during the SAMPLE/PRELOAD JTAG instruction.
Configuration clock source Specifies the clock source for device initialization (the duration between CONF_DONE signal went high and before INIT_DONE signal goes high).

For AS x1 or AS x4 configuration mode, you can select either Internal Oscillator or CLKUSR pin only. The DCLK pin is an illegal option for AS mode. In 14 nm device families, only Internal Oscillator or OSC_CLK_1 pins are available.

Device initialization clock source Specifies the clock source for device initialization (the duration between CONF_DONE signal went high and before INIT_DONE signal goes high).

For AS x1 or AS x4 configuration mode, you can select either Internal Oscillator or CLKUSR pin only. The DCLK pin is an illegal option for AS mode. In 14 nm device families, only Internal Oscillator or OSC_CLK_1 pins are available.

Configuration Options

Allow you to specify the configuration scheme, configuration device and pin options, serial clock source, and other options for subsequent device configuration with your programming bitstream. To access these settings, click Assignments > Device > Device and Pin Options > Configuration. Disabled options are unavailable for the current device or configuration mode.

Table 13.  Configuration Options
Option Description
Configuration scheme Specifies the scheme of configuration for generation of appropriate primary and secondary programming files, such as Active Serial x4. Only options appropriate for the current Configuration Scheme are available.
Configuration Device Allows you to specify options for an external configuration device that stores and loads configuration data.
  • Configuration device I/O voltage—specifies the VCCIO voltage of the configuration pins for the current configuration scheme of the target device. This option is available for supported device families.
  • Force VCCIO voltage to be compatible with configuration I/O voltage—forces the VCCIO voltage of the configuration pins to be the same as the configuration device I/O voltage. If you turn off this option, the VCCIO voltage of the configuration pins may vary depending on the I/O standards used in the I/O banks containing the configuration pins. This option is available for supported device families.
Configuration Pin Options Enables or disables operation of specific device configuration pins for status monitoring, SEU error detection, CvP, and other configuration pin options.
Generate compressed bitstreams Generates compressed bitstreams and enables bitstream decompression in the target device.
Active serial clock source Specifies the configuration clock source for Active Serial programming. Options range from 12.5 MHz to 100 MHz.
VID Operation Mode Enables Voltage IDentification logic in the target device with selected operation mode. The available options are PMBus Master or PMBus Slave.
HPS/FPGA configuration order For hard processor system (HPS) configuration, specifies the order of configuration between the HPS and FPGA. The options are HPS First, After INIT_DONE, and When requested by FPGA.
HPS debug access port
  • Disabled—the HPS JTAG is not enabled.
  • HPS Pins—the HPS JTAG is routed to the HPS dedicated I/O.
  • SDM Pins—the HPS JTAG is chained to the FPGA JTAG.
Disable Register Power-Up Initialization Specifies whether the Assembler generates a bit stream with register power-up initialization.
Table 14.  Assembler Security SettingsFor Intel® Stratix® 10 devices, specifies settings for programming bitstream authentication, encryption, scrambling, and other eFuse enabled security options. To access these settings, click Assignments > Device > Device and Pin Options > Security. Disabled options are unavailable for the current device or configuration mode.
Option Description
Quartus Key File Specifies the first level signature chain file (.qky) that you generate. This chain includes the root key (.pem) and one or more design signing keys (.pem) required to sign the bitstream and allow access to the FPGA when using authentication or encryption.
Encryption key storage select Specifies the location that stores the .qek key file. You can select either Battery Backup RAM or eFuses for storage.
Encryption update ratio Specifies the ratio of configuration bits compared to the number of key updates required for bitstream decryption. You can select either 31:1 (the key must change 1 time every 31 bits) or Disabled (no update required). Encryption supports up to 20 intermediate keys.
Enable scrambling Scrambles the configuration bitstream.
More Options Opens the More Security Options dialog box for specifying additional physical security options.

Configuration PIN Dialog Box

For Intel® Stratix® 10 devices, allows you to enable or disable specific configuration pins. For example, you can enable the CvP_CONFDONE pin, which indicates that the device finished core programming in Configuration via Protocol mode. To access these settings, click Assignments > Device > Device and Pin Options > Configuration Pin Options. Disabled options are unavailable for the current device or configuration mode.

Table 15.  Configuration PIN Dialog Box
Option Values Description
USE PWRMGT_SCL output SDM_1O0| SDM_IO14

This is a required PMBus interface for the power management when the VID operation mode is the PMBus Master or PMBus Slave mode.

Disable this pin for a non-SmartVID device.

Intel® recommends using the SDM_IO14 pin for this function.

Use PWRMGT_SDA output SDM_1O11| SDM_1O12|SDM_1O16

This is a required PMBus interface for the power management when the VID operation mode is the PMBus Master or PMBus Slave mode.

Disable this pin for a non-SmartVID device.

Intel® recommends using the SDM_IO11 pin for this function.

Use PWRMGT_ALERT output SDM_1O0|SDM_1O12

This is a required PMBus interface for the power management that is used only in the PMBus Slave mode.

Disable this pin for a non-SmartVID device.

Intel® recommends using the SDM_IO12 pin for this function.

USE CONF_DONE output SDM_100, SDM_1010 - SDM_1016 Implement CONF_DONE using appropriate configuration pin resource.
USE INIT_DONE output SDM_100, SDM_1010 - SDM_1016 Enables the INIT_DONE pin, which allows you to externally monitor when initialization is completed and the device is in user mode. If this option is turned off, the INIT_DONE pin is disabled when the device operates in user mode and is available as a user I/O pin.
USE CVPCONF_DONE output SDM_100, SDM_1010 - SDM_1016 Enables the CVP_CONFDONE pin, which indicates that the device finished core programming in Configuration via Protocol mode. If this option is turned off, the CVP_CONFDONE pin is disabled when the device operates in user mode and is available as a user I/O pin.
USE SEU_ERROR output SDM_100, SDM_1010 - SDM_1016 Enables the SEU_ERROR pin for use in single event upset error detection.
USE UIB CATTRIP output SDM_100, SDM_1010 - SDM_1016 Enables UIB_CATTRIP output to indicate an extreme over-temperature conditioning resulted from UIB usage.
USE HPS cold nreset SDM_100, SDM_1010 - SDM_1016 An optional reset input that cold resets only the HPS and is configured for bidirectional operation.
Direct to factory image SDM_100, SDM_1010 - SDM_1016 If this pin asserted then device loads the factory image as the first image after boot without attempting to load any application image.
USE DATA LOCK output SDM_100, SDM_1010 - SDM_1016 Output to indicate DIBs on both die in the same package is ready for data transfer.
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