Cyclone® V Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* Solutions User Guide

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ID 683494
Date 10/24/2024
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM Cyclone V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Reset and Clocks 7. Interrupts for Endpoints 8. Error Handling A. PCI Express Protocol Stack 9. Design Implementation 10. Additional Features 11. Transceiver PHY IP Reconfiguration 12. Debugging B. Frequently Asked Questions for PCI Express C. Lane Initialization and Reversal D. Document Revision History
1. Datasheet x
1.1. Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Example Designs 1.7. IP Core Verification 1.8. Performance and Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM Cyclone V Hard IP for PCI Express x
2.1. Running Platform Designer 2.2. Generating the Example Design 2.3. Running a Gate-Level Simulation 2.4. Simulating the Single DWord Design 2.5. Understanding Channel Placement Guidelines 2.6. Generating Synthesis Files 2.7. Compiling the Design in the Quartus® Prime Software 2.8. Programming a Device
3. Parameter Settings x
3.1. Avalon-MM System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. Device Capabilities 3.5. Error Reporting 3.6. Link Capabilities 3.7. MSI and MSI-X Capabilities 3.8. Power Management 3.9. Avalon Memory‑Mapped System Settings
4. Interfaces and Signal Descriptions x
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 4.2. Clock Signals 4.3. Reset Signals 4.4. Hard IP Status 4.5. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 4.6. Physical Layer Interface Signals
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
4.1.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 4.1.2. Bursting and Non-Bursting Avalon® -MM Module Signals 4.1.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
4.6. Physical Layer Interface Signals x
4.6.1. Transceiver Reconfiguration 4.6.2. Hard IP Status Extension 4.6.3. Serial Interface Signals 4.6.4. PIPE Interface Signals 4.6.5. Test Signals
4.6.2. Hard IP Status Extension x
4.6.2.1. Configuration Space Register Access 4.6.2.2. Configuration Space Register Access Timing
4.6.3. Serial Interface Signals x
4.6.3.1. Physical Layout of Hard IP in Cyclone V Devices 4.6.3.2. Channel Placement in Cyclone V Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 5.8. Programming Model for Avalon-MM Root Port 5.9. Uncorrectable Internal Error Mask Register 5.10. Uncorrectable Internal Error Status Register 5.11. Correctable Internal Error Mask Register 5.12. Correctable Internal Error Status Register
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
5.7.1. Avalon-MM to PCI Express Interrupt Registers
5.7.1. Avalon-MM to PCI Express Interrupt Registers x
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 5.7.1.3. PCI Express Mailbox Registers 5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 5.7.1.6. Avalon-MM Mailbox Registers 5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
5.8. Programming Model for Avalon-MM Root Port x
5.8.1. Sending a Write TLP 5.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 5.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 5.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 5.8.5. Root Port TLP Data Registers
6. Reset and Clocks x
6.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 6.2. Clocks
6.2. Clocks x
6.2.1. Clock Domains 6.2.2. Clock Summary
6.2.1. Clock Domains x
6.2.1.1. pclk 6.2.1.2. coreclkout_hip 6.2.1.3. pld_clk
7. Interrupts for Endpoints x
7.1. Enabling MSI or Legacy Interrupts 7.2. Generation of Avalon-MM Interrupts 7.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Transceiver Reconfiguration A.1.4. Interrupts A.1.5. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block
9. Design Implementation x
9.1. Making Analog QSF Assignments Using the Assignment Editor 9.2. Making Pin Assignments 9.3. Recommended Reset Sequence to Avoid Link Training Issues
10. Additional Features x
10.1. Configuration over Protocol (CvP) 10.2. Autonomous Mode 10.3. ECRC
10.2. Autonomous Mode x
10.2.1. Enabling Autonomous Mode 10.2.2. Enabling CvP Initialization
10.3. ECRC x
10.3.1. ECRC on the RX Path 10.3.2. ECRC on the TX Path
11. Transceiver PHY IP Reconfiguration x
11.1. Connecting the Transceiver Reconfiguration Controller IP Core 11.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
12. Debugging x
12.1. Hardware Bring-Up Issues 12.2. Link Training 12.3. Use Third-Party PCIe Analyzer 12.4. BIOS Enumeration Issues
D. Document Revision History x
D.1. Arria® V and Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History
1. Datasheet
2. Getting Started with the Avalon-MM Cyclone V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Reset and Clocks
7. Interrupts for Endpoints
8. Error Handling
A. PCI Express Protocol Stack
9. Design Implementation
10. Additional Features
11. Transceiver PHY IP Reconfiguration
12. Debugging
B. Frequently Asked Questions for PCI Express
C. Lane Initialization and Reversal
D. Document Revision History

8.3. Transaction Layer Errors

Table 70.  Errors Detected by the Transaction Layer

Error

Type

Description

Poisoned TLP received

Uncorrectable (non-fatal)

This error occurs if a received Transaction Layer Packet has the EP poison bit set.

The received TLP is passed to the Application Layer and the Application Layer logic must take appropriate action in response to the poisoned TLP. Refer to “2.7.2.2 Rules for Use of Data Poisoning” in the PCI Express Base Specification for more information about poisoned TLPs.

ECRC check failed  (1)

Uncorrectable (non-fatal)

This error is caused by an ECRC check failing despite the fact that the TLP is not malformed and the LCRC check is valid.

The Hard IP block handles this TLP automatically. If the TLP is a non‑posted request, the Hard IP block generates a completion with completer abort status. In all cases the TLP is deleted in the Hard IP block and not presented to the Application Layer.

Unsupported Request for Endpoints

Uncorrectable (non-fatal)

This error occurs whenever a component receives any of the following Unsupported Requests:

  • Type 0 Configuration Requests for a non-existing function.
  • Completion transaction for which the Requester ID does not match the bus, device and function number.
  • Unsupported message.
  • A Type 1 Configuration Request TLP for the TLP from the PCIe link.
  • A locked memory read (MEMRDLK) on native Endpoint.
  • A locked completion transaction.
  • A 64-bit memory transaction in which the 32 MSBs of an address are set to 0.
  • A memory or I/O transaction for which there is no BAR match.
  • A memory transaction when the Memory Space Enable bit (bit [1] of the PCI Command register at Configuration Space offset 0x4) is set to 0.
  • A poisoned configuration write request (CfgWr0)

In all cases the TLP is deleted in the Hard IP block and not presented to the Application Layer. If the TLP is a non-posted request, the Hard IP block generates a completion with Unsupported Request status.

Unsupported Requests for Root Port

Uncorrectable (fatal)

This error occurs whenever a component receives an Unsupported Request including:

  • Unsupported message
  • A Type 0 Configuration Request TLP
  • A 64-bit memory transaction which the 32 MSBs of an address are set to 0.
  • A memory transaction that does not match the address range defined by the Base and Limit Address registers

Completion timeout

Uncorrectable (non-fatal)

This error occurs when a request originating from the Application Layer does not generate a corresponding completion TLP within the established time. It is the responsibility of the Application Layer logic to provide the completion timeout mechanism. The completion timeout should be reported from the Transaction Layer using the cpl_err[0] signal.

Completer abort  (1)

Uncorrectable (non-fatal)

The Application Layer reports this error using the cpl_err[2]signal when it aborts receipt of a TLP.

Unexpected completion

Uncorrectable (non-fatal)

This error is caused by an unexpected completion transaction. The Hard IP block handles the following conditions:

  • The Requester ID in the completion packet does not match the Configured ID of the Endpoint.
  • The completion packet has an invalid tag number. (Typically, the tag used in the completion packet exceeds the number of tags specified.)
  • The completion packet has a tag that does not match an outstanding request.
  • The completion packet for a request that was to I/O or Configuration Space has a length greater than 1 dword.
  • The completion status is Configuration Retry Status (CRS) in response to a request that was not to Configuration Space.

In all of the above cases, the TLP is not presented to the Application Layer; the Hard IP block deletes it.

The Application Layer can detect and report other unexpected completion conditions using the cpl_err[2] signal. For example, the Application Layer can report cases where the total length of the received successful completions do not match the original read request length.

Receiver overflow   (1)

Uncorrectable (fatal)

This error occurs when a component receives a TLP that violates the FC credits allocated for this type of TLP. In all cases the hard IP block deletes the TLP and it is not presented to the Application Layer.

Flow control protocol error (FCPE)  (1)

Uncorrectable (fatal)

This error occurs when a component does not receive update flow control credits with the 200 µs limit.

Malformed TLP

Uncorrectable (fatal)

This error is caused by any of the following conditions:

  • The data payload of a received TLP exceeds the maximum payload size.
  • The TD field is asserted but no TLP digest exists, or a TLP digest exists but the TD bit of the PCI Express request header packet is not asserted.
  • A TLP violates a byte enable rule. The Hard IP block checks for this violation, which is considered optional by the PCI Express specifications.
  • A TLP in which the type and length fields do not correspond with the total length of the TLP.
  • A TLP in which the combination of format and type is not specified by the PCI Express specification.
  • A request specifies an address/length combination that causes a memory space access to exceed a 4  KB boundary. The Hard IP block checks for this violation, which is considered optional by the PCI Express specification.
  • Messages, such as Assert_INTX, Power Management, Error Signaling, Unlock, and Set Power Slot Limit, must be transmitted across the default traffic class.

The Hard IP block deletes the malformed TLP; it is not presented to the Application Layer.

Note:

  1. Considered optional by the PCI Express Base Specification Revision.
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