Cyclone® V Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* Solutions User Guide

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ID 683494
Date 10/24/2024
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM Cyclone V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Reset and Clocks 7. Interrupts for Endpoints 8. Error Handling A. PCI Express Protocol Stack 9. Design Implementation 10. Additional Features 11. Transceiver PHY IP Reconfiguration 12. Debugging B. Frequently Asked Questions for PCI Express C. Lane Initialization and Reversal D. Document Revision History
1. Datasheet x
1.1. Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Example Designs 1.7. IP Core Verification 1.8. Performance and Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM Cyclone V Hard IP for PCI Express x
2.1. Running Platform Designer 2.2. Generating the Example Design 2.3. Running a Gate-Level Simulation 2.4. Simulating the Single DWord Design 2.5. Understanding Channel Placement Guidelines 2.6. Generating Synthesis Files 2.7. Compiling the Design in the Quartus® Prime Software 2.8. Programming a Device
3. Parameter Settings x
3.1. Avalon-MM System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. Device Capabilities 3.5. Error Reporting 3.6. Link Capabilities 3.7. MSI and MSI-X Capabilities 3.8. Power Management 3.9. Avalon Memory‑Mapped System Settings
4. Interfaces and Signal Descriptions x
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 4.2. Clock Signals 4.3. Reset Signals 4.4. Hard IP Status 4.5. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 4.6. Physical Layer Interface Signals
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
4.1.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 4.1.2. Bursting and Non-Bursting Avalon® -MM Module Signals 4.1.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
4.6. Physical Layer Interface Signals x
4.6.1. Transceiver Reconfiguration 4.6.2. Hard IP Status Extension 4.6.3. Serial Interface Signals 4.6.4. PIPE Interface Signals 4.6.5. Test Signals
4.6.2. Hard IP Status Extension x
4.6.2.1. Configuration Space Register Access 4.6.2.2. Configuration Space Register Access Timing
4.6.3. Serial Interface Signals x
4.6.3.1. Physical Layout of Hard IP in Cyclone V Devices 4.6.3.2. Channel Placement in Cyclone V Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 5.8. Programming Model for Avalon-MM Root Port 5.9. Uncorrectable Internal Error Mask Register 5.10. Uncorrectable Internal Error Status Register 5.11. Correctable Internal Error Mask Register 5.12. Correctable Internal Error Status Register
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
5.7.1. Avalon-MM to PCI Express Interrupt Registers
5.7.1. Avalon-MM to PCI Express Interrupt Registers x
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 5.7.1.3. PCI Express Mailbox Registers 5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 5.7.1.6. Avalon-MM Mailbox Registers 5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
5.8. Programming Model for Avalon-MM Root Port x
5.8.1. Sending a Write TLP 5.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 5.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 5.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 5.8.5. Root Port TLP Data Registers
6. Reset and Clocks x
6.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 6.2. Clocks
6.2. Clocks x
6.2.1. Clock Domains 6.2.2. Clock Summary
6.2.1. Clock Domains x
6.2.1.1. pclk 6.2.1.2. coreclkout_hip 6.2.1.3. pld_clk
7. Interrupts for Endpoints x
7.1. Enabling MSI or Legacy Interrupts 7.2. Generation of Avalon-MM Interrupts 7.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Transceiver Reconfiguration A.1.4. Interrupts A.1.5. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block
9. Design Implementation x
9.1. Making Analog QSF Assignments Using the Assignment Editor 9.2. Making Pin Assignments 9.3. Recommended Reset Sequence to Avoid Link Training Issues
10. Additional Features x
10.1. Configuration over Protocol (CvP) 10.2. Autonomous Mode 10.3. ECRC
10.2. Autonomous Mode x
10.2.1. Enabling Autonomous Mode 10.2.2. Enabling CvP Initialization
10.3. ECRC x
10.3.1. ECRC on the RX Path 10.3.2. ECRC on the TX Path
11. Transceiver PHY IP Reconfiguration x
11.1. Connecting the Transceiver Reconfiguration Controller IP Core 11.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
12. Debugging x
12.1. Hardware Bring-Up Issues 12.2. Link Training 12.3. Use Third-Party PCIe Analyzer 12.4. BIOS Enumeration Issues
D. Document Revision History x
D.1. Arria® V and Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History
1. Datasheet
2. Getting Started with the Avalon-MM Cyclone V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Reset and Clocks
7. Interrupts for Endpoints
8. Error Handling
A. PCI Express Protocol Stack
9. Design Implementation
10. Additional Features
11. Transceiver PHY IP Reconfiguration
12. Debugging
B. Frequently Asked Questions for PCI Express
C. Lane Initialization and Reversal
D. Document Revision History

D.1. Arria® V and Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History

Date

Version

Changes Made

2024.10.24 17.1 Updated the text and timing diagrams in Interrupts for Endpoints when Multiple MSI/MSI-X Support is Enabled to reflect that IntxAck_o is tied to 1'b0 in Arria® V and Cyclone® V devices.
2020.03.19 17.1 Updated the reset sequence and descriptions in Reset and Clocks to show that reset_status is the output that can be used to reset the Application Layer logic.
2017.11.06 17.1 Made the following changes to the user guide.
  • Corrected Feature Comparison for all Hard IP for PCI Express IP Core table: The Avalon-MM interface does not automatically handle out-of-order completions.
2017.05.21 17.0 Made the following changes:
  • Corrected support for Completion with Data (CplD) in TLP Support Comparison for all Hard IP for PCI Express IP Cores. The Avalon-MM interface supports this TLP type.
  • Corrected default values for the Uncorrectable Internal Error Mask Register and Correctable Internal Error Mask Register registers.

  • Revised discussion of Application Layer Interrupt Handler Module to include legacy interrupt generation.

  • Added Configuration Space Register Access topic which shows the data that is multiplexed on the tl_cfg_ctl bus.

2017.05.08 16.1 Made the following changes:
  • Corrected description of the figure entitled, Cyclone V GX/GT/ST/ST Devices with 9 or 12 Transceiver Channels and 2 PCIe Cores.
2016.10.31 16.1 Made the following changes:
  • Added topic explaining how to switch between serial and PIPE simulations.
  • Corrected the number of tags supported in the Feature Comparison for all Hard IP for PCI Express IP Cores table.
  • Added PCIe bifurcation to the Feature Comparison for all Hard IP for PCI Express IP Cores table. PCI bifurcation is not supported.
  • Corrected description and timing diagram for the tl_cfg* interface in the Configuration Space Register Access Timing topic.
  • Added instructions for turning on autonomous mode in the Quartus Prime software.
2016.05.01 16.0 Made the following changes:
  • Clarified optimal read request size for typical systems that include the Avalon-MM TX slave interface.
  • Added figure for TX 3-dword header with qword aligned data
  • Corrected minor errors and typos.
2015.11.30 15.1 Made the following changes to the user guide:
  • Added TX_FIFO_EMPTY bit to the PCI Express to Avalon-MM Interrupt Status register for Legacy Endpoints only. This bit is set when the TX internal buffer is ready.
  • Enhanced the descriptions in Avalon-MM-to-PCI Express Address Translation Table.
  • Enhanced the definition of npor.
  • Added definition of Address width of accessible PCIe memory space in Parameter Settings chapter.
  • Added description of the Altera PCIe Reconfig Driver in the Connecting the Transceiver Reconfiguration Controller IP Core topic.
  • Clarified Application Layer requirements for multiple and single MSI and MSI-X support.
  • Corrected width of AVL_IRQ. It is 16 bits.
  • Added the following restriction for 128-bit Avalon-MM bridge. Supported patterns for byte enables must be at the dword granularity.
  • Clarified Avalon-MM addressing for various data widths.
  • Added signal definition for tl_cfg_ctl which was missing.
  • Removed the dlup signal. This signal is no longer part of the Hard IP Status interface.
  • Added note explaining that the Getting Started design examples do not generate all the files necessary to download to an Altera FPGA Development Kit. Provided link to AN456 PCI Express High Performance Reference Design that includes all necessary files.
2014.12.15 14.1 Made the following changes to the user guide:
  • In the figured titled Specifying the Number of Transceiver Interfaces for Arria V and Cyclone V Devices, removed the Calibrate duty cycle during power up. Duty cycle calibration occurs during Gen1 to Gen2 speed changes. This is no longer a parameter than you can turn on and off.
  • Corrected discussion of soft and hard reset controllers. The hardened reset controller is used for Arria V and Cyclone V devices.
  • Restricted Recommended Speed Grades for Cyclone V devices to GT parts for both the Gen1 and Gen2 data rates.
  • Added statement that the bottom left hard IP block includes the CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom right block.
  • Corrected bit definitions for CvP Status register.
  • Updated definition of CVP_NUMCLKS in the CvP Mode Control register.
  • Added definitions for test_in[2], test_in[6] and test_in[7].
  • Removed requirement that TxsWrite_i be asserted continuously throughout a write burst. TxsWrite_i may be deasserted and reasserted during a burst.
  • Added figure showing connectivity for the Transceiver Reconfiguration Controller and Altera PCIe Reconfig Driver IP Cores to the Getting Started chapter.
  • Removed Maximum and High settings from the RX Buffer credit allocation -performance for received requests setting. These settings are not available for the Avalon-MM interface and could lead to data corruption.
  • Revised Receiving a Completion TLP under Programming Model for Avalon-MM Root Port to cover read and non-posted completions.
2014.06.30 14.0

Added the following features to the Cyclone V Avalon-MM Hard IP for PCI Express:

  • Added access to selected Configuration Space registers and link status registers through the optional Control Register Access (CRA) Avalon-MM slave port.
  • Added optional hard IP status bus that includes signals necessary to connect the Transceiver Reconfiguration Controller IP Core.
  • Added optional hard IP status extension bus which includes signals that are useful for debugging, including: link training, status, error, and Configuration Space signals.
  • For TxsByteEnable_i[<w>-1:0], added restrictions on the legal patterns of enabled and disabled bytes.
  • Clarified the behavior of the TxsWaitrequest_o signal.

Made the following changes to the user guide:

  • Created separate user guides for variants using the Avalon-MM, Avalon-ST, and Avalon-MM with DMA interfaces to the Application Layer.
  • Corrected frequency range for hip_reconfig_clk. It should be 100-125 MHz.
  • Simplified the Getting Started chapter. It copies the Gen1 x4 example from the install directory and does not include step-by-step instructions to recreate the design.
  • Added Next Steps in Creating a Design for PCI Express to Datasheet chapter.
  • Removed references to the MegaWizard® Plug-In Manager. In 14.0 the IP Parameter Editor Powered by Platform Designer has replaced the MegaWizard Plug-In Manager.
  • Corrected channel placement diagrams for Cyclone V Devices .
  • Added definition for test_in[6] and link to Knowledge Base Solution on observing the PIPE interface signals on the test_out bus.
  • Clarified that the Avalon-MM Bridge does not generate out-of-order Avalon-MM-to-PCI Express Read Completions even to different BARs.
  • Removed reconfig_busy port from connect between PHY IP Core for PCI Express and the Transceiver Reconfiguration Controller in the Altera Transceiver Reconfiguration Controller Connectivity figure. The Transceiver Reconfiguration Controller drives reconfig_busy port to the Altera PCIe Reconfig Driver.
  • Updated Recommended Speed Grades table for the Gen2 data rate. For Cyclone V devices, the Gen2 data rate requires a Cyclone V GT device. GT devices are available only for the –7 speed grade.
  • Added fact that DCD calibration is required for Gen2 data rate in the description of the transceiver reconfiguration signals. Updated figure showing Transceiver Reconfiguration Controller parameter editor.
  • Removed reference to Gen2 x1 62.5 MHz configuration in Application Layer Clock Frequency for All Combination of Link Width, Data Rate and Application Layer Interface Widths table. This configuration is not supported.
  • Added description of TxsWaitRequest signal which is asserted when the Avalon-MM bridge has eight outstanding read requests.
  • Added sections on making analog QSF and pin assignments.
  • Enhanced definition of Device ID and Sub-system Vendor ID to say that these registers are only valid in the Type 0 (Endpoint) Configuration Space.
  • Improved figure showing multiple MSI and MSI-X support and added reference to example on Altera wiki.
  • Removed references to the ATX PLL. This PLL is not available for Cyclone V
  • Updated Power Supply Voltage Requirements table.
  • Revised Physical Placement of Hard IP in Cyclone V Devices figures.
  • For Cyclone V devices changed speed grade recommendation to use GT devices for both the Gen1 and Gen2 data rate.
2014.12.20 13.1 Made the following changes:
  • Added constraints for refclk when CvP is enabled.
  • Corrected location information for nPERSTL*.
  • Corrected definition of test_in[4:1].
  • In Debugging chapter, under changing between soft and hard reset controller, changed the file name in which the parameter hip_hard_reset_hwtclmust be set to 0 to use the soft reset controller.
  • Added explanation of channel labeling for serial data. The Hard IP on the left side of the device must connect to the appropriate channels on the left side of the device, and so on.
  • Corrected connection for the Transceiver Reconfiguration Controller IP Core reset signal, alt_xcvr_reconfig_0 mgmt_rst_reset, Getting Started with the Avalon-MM Arria V Hard IP for PCI Express. This reset input connects to clk_0 clk_reset.
  • Added definition of nreset_status for variants using the Avalon-MM interface.
  • In Transaction Layer Routing Rules and Programming Model for Avalon-MM Root Port , added the fact that Type 0 Configuration Requests sent to the Root Port are not filtered by the device number. Application Layer software must filter out requests for device number greater than 0.
  • Added Recommended Reset Sequence to Avoid Link Training Issues to the Debugging chapter.
  • Added limitation for RxmIrq_<n>_i[<m>:0] when interrupts are received on consecutive cycles.
  • Updated timing diagram for tl_cfg_ctl.
  • Removed I/O Read Request and I/O Write Requests from TLPs supported for Avalon-MM interface.
  • Added note that the LTSSM interface can be used for Signal Tap debugging.
  • Added restriction on the use of dynamic transceiver reconfiguration when CvP is enabled.

2014.05.06

13.0

Made the following changes:
  • Timing models are now final.
  • Added instructions for running the Single Dword variant.
  • Corrected definition of test_in[4:1]. This vector must be set to 4’b0100.
  • Corrected connection for mgmt_clk_clk in Figure 3-2.
  • Corrected definition of nPERSTL*. The device has 1 nPERSTL* pin for each instance of the Hard IP for PCI Express in the device.
  • Corrected feature comparison table in Datasheet chapter. The Avalon-MM Hard IP for PCI Express IP Core does not support legacy endpoints.
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