AN 114: Board Design Guidelines for Intel Programmable Device Packages

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ID 683481
Date 5/27/2022
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Document Table of Contents
Document Table of Contents x
1. AN 114: Board Design Guidelines for Intel® Programmable Device Packages
1. AN 114: Board Design Guidelines for Intel® Programmable Device Packages x
1.1. Overview of BGA Packages 1.2. PCB Layout Terminology 1.3. PCB Layout for High-Density BGA Packages 1.4. Document Revision History for AN 114: Board Design Guidelines for Intel® Programmable Device Packages
1.2. PCB Layout Terminology x
1.2.1. Escape Routing 1.2.2. Multi-Layer PCBs 1.2.3. Vias 1.2.4. Via Capture Pad 1.2.5. Surface Land Pad 1.2.6. Stringer
1.2.5. Surface Land Pad x
1.2.5.1. Non Solder Mask Defined Pad 1.2.5.2. Solder Mask Defined Pad
1.3. PCB Layout for High-Density BGA Packages x
1.3.1. Surface Land Pad Dimension 1.3.2. Via Capture Pad Layout and Dimension 1.3.3. Signal Line Space and Trace Width 1.3.4. Number of PCB Layers
1.3.4. Number of PCB Layers x
1.3.4.1. Sample PCB Layout for 1.00-mm Flip-Chip BGA and 0.80-mm UBGA (BT Substrate) 1.3.4.2. Sample PCB Routing Scheme on 6 Layers for 0.5-mm 484-pin MBGA 1.3.4.3. Sample PCB Routing Scheme on 3 Layers for 0.5-mm 383-pin MBGA 1.3.4.4. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 301-pin MBGA 1.3.4.5. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 153-pin MBGA 1.3.4.6. Sample PCB Routing Scheme on 4 Layers for 0.5-mm 144-pin MBGA 1.3.4.7. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 256-pin and 100-pin MBGAs 1.3.4.8. Sample PCB Routing Scheme on 4 Layers for 0.4-mm 81-pin VBGA (also known as WLCSP) 1.3.4.9. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 68-pin MBGA 1.3.4.10. Sample PCB Routing Scheme on 2 Layers for 0.4-mm 36-pin VBGA (also known as WLCSP) 1.3.4.11. Sample PCB Routing Scheme on 3 Layers for 0.8-mm 324-pin UBGA 1.3.4.12. Sample PCB Routing Scheme on 3 Layers for 0.8-mm 169-pin UBGA
1. AN 114: Board Design Guidelines for Intel® Programmable Device Packages

1.3.2. Via Capture Pad Layout and Dimension

The size and layout of via capture pads affect the amount of space available for escape routing. In general, you can lay out via capture pads in the following two ways:

  • In-line with the surface land pads
  • Diagonal to the surface land pads

The decision to place the via capture pads diagonally or in-line with the surface land pads is based on the following factors:

  • Diameter of the via capture pad
  • Stringer length
  • Clearance between via capture pad and surface land pad

Use Figure 9 and Table 5 to guide the layout of 1.00-mm pitch BGA packages using NSMD land pads.

Figure 9. Placement of Via Capture Pad for 1.00-mm Flip-Chip BGA NSMD Land PadsThis is not applicable for Intel® Stratix® 10 devices.

If your PCB design guidelines do not conform to either equation in the following table, contact Intel® Premier Support for further assistance.

Table 5.  Formula for Via Layouts for 1.00-mm Flip-Chip BGA NSMD Land PadsThis is not applicable for Intel® Stratix® 10 devices.
Layout Formula
In-line a + c + d <= 0.53 mm
Diagonally a + c + d <= 0.94 mm

Note that Table 5 shows that you can place a larger via capture pad diagonally than in-line with the surface land pads.

Use Figure 10 and Table 6 to guide the layout of 0.80-mm pitch U BGA packages using NSMD land pads.

Figure 10. Placement of Via Capture Pad for 0.80-mm UBGA (BT Substrate) NSMD Land Pads

If your PCB design guidelines do not conform to either equation in the following table, contact mySupport for further assistance.

Table 6.  Formula for Via Layouts for 0.80-mm UBGA (BT Substrate) NSMD Land Pads
Layout Formula
In-line a + c + d <= 0.46 mm
Diagonally a + c + d <= 0.68 mm

Note that Table 6 shows that you can place a larger via capture pad diagonally than in-line with the surface land pads.

Figure 11. Placement of Via Capture Pad for 0.5-mm MBGA Land Pads

For 0.5-mm pitch, Intel® recommends you to use microvia technology of 0.10-mm via drill in the pad, and route trace in the inner layers.

Figure 12. Placement of Via Capture Pad for 0.4-mm VBGA (also known as WLCSP) Land Pads

For 0.4-mm pitch, Intel® recommends you to use microvia technology of 0.10-mm via drill in the pad, and route trace in the inner layers.

Via capture pad size also affects how many traces can be routed on a PCB. Figure 13 shows sample layouts of typical and premium via capture pads. The typical layout shows a via capture pad size of 0.660 mm, a via size of 0.254 mm, and an inner space and trace of 0.102 mm. With this layout, only one trace can be routed between the vias. If more traces are required, you must reduce the via capture pad size or the space and trace size.

The premium layout shows a via capture pad size of 0.508 mm, a via size of 0.203 mm, and an inner space and trace of 0.076 mm. This layout provides enough space to route two traces between the vias.

Figure 13. Typical and Premium Via Capture Pad Sizes for a 1.00-mm Flip-Chip BGAThis is not applicable for Intel® Stratix® 10 devices.

The following table lists the typical and premium layout specifications for a 1.00 mm Flip-Chip BGA used by most PCB vendors.

Table 7.  PCB Vendor Specifications for a 1.00-mm Flip-Chip BGAThis is not applicable for Intel® Stratix® 10 devices.
Specification Typical (mm) Premium (mm) PCB Thickness >1.5 mm Premium (mm) PCB Thickness <= 1.5 mm
Trace and space width 0.1/0.1 0.076/0.076 0.076/0.076
Drilled hole diameter 0.305 0.254 0.150
Finished via diameter 0.254 0.203 0.100
Via capture pad 0.660 0.508 0.275
Aspect ratio 7:1 10:1 10:1

Figure 14 shows sample layouts of typical and premium via capture pads. The typical layout shows a via capture pad size of 0.495 mm, a via size of 0.254 mm, and an inner space and trace of 0.102 mm. With this layout, only one trace can be routed between the vias. If more traces are required, you must reduce the via capture pad size or the space and trace size.

The premium layout shows a via capture pad size of 0.419 mm, a via size of 0.165 mm, and an inner space and trace of 0.076 mm. This layout provides enough space to route two traces between the vias.

Figure 14. Typical and Premium Via Capture Pad Sizes for a 0.80-mm UBGA (BT Substrate)

The following table lists the typical and premium layout specifications for a 0.80 mm UBGA (BT Substrate) used by most PCB vendors.

Table 8.  PCB Vendor Specifications for a 0.80-mm UBGA (BT Substrate)
Specification Typical (mm) Premium (mm) PCB Thickness >1.5 mm Premium (mm) PCB Thickness <= 1.5 mm
Trace and space width 0.1/0.1 0.076/0.076 0.076/0.076
Drilled hole diameter 0.381 0.330 0.254
Finished via diameter 0.254 0.165 0.127
Via capture pad 0.495 0.419 0.381
Aspect ratio 8:1 25:1 12:1

Figure 15 shows sample layout of typical via capture pad. The typical layout shows a via capture pad size of 0.25 mm, a via size of 0.10 mm, and an inner space and trace of 0.068 mm.

Figure 15. Typical Via Capture Pad Size for a 0.50-mm MBGA

The following table lists the typical layout specifications for a 0.50-mm MBGA used by most PCB vendors.

Table 9.  PCB Vendor Specification for a 0.50-mm MBGA
Specification Typical (mm)
Trace and space width 0.086
Finished via diameter 0.10
Via capture pad 0.25

Figure 16 shows sample layout of typical via capture pad. The typical layout shows a via capture pad size of 0.25 mm and a via size of 0.10 mm. For the 0.40-mm pitch, there is not enough space to route trace in the component layer, because the minimum trace width is 0.075 mm and the minimum gap between the trace and pad is 0.086 mm.

Figure 16. Typical Via Capture Pad Size for a 0.40-mm VBGA (also known as WLCSP)

For detailed information on drill sizes, via sizes, space and trace sizes, or via capture pad sizes, contact your PCB vendor directly.

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