AN 114: Board Design Guidelines for Intel Programmable Device Packages

Download PDF
ID 683481
Date 5/27/2022
Public
Document Table of Contents
Document Table of Contents x
1. AN 114: Board Design Guidelines for Intel® Programmable Device Packages
1. AN 114: Board Design Guidelines for Intel® Programmable Device Packages x
1.1. Overview of BGA Packages 1.2. PCB Layout Terminology 1.3. PCB Layout for High-Density BGA Packages 1.4. Document Revision History for AN 114: Board Design Guidelines for Intel® Programmable Device Packages
1.2. PCB Layout Terminology x
1.2.1. Escape Routing 1.2.2. Multi-Layer PCBs 1.2.3. Vias 1.2.4. Via Capture Pad 1.2.5. Surface Land Pad 1.2.6. Stringer
1.2.5. Surface Land Pad x
1.2.5.1. Non Solder Mask Defined Pad 1.2.5.2. Solder Mask Defined Pad
1.3. PCB Layout for High-Density BGA Packages x
1.3.1. Surface Land Pad Dimension 1.3.2. Via Capture Pad Layout and Dimension 1.3.3. Signal Line Space and Trace Width 1.3.4. Number of PCB Layers
1.3.4. Number of PCB Layers x
1.3.4.1. Sample PCB Layout for 1.00-mm Flip-Chip BGA and 0.80-mm UBGA (BT Substrate) 1.3.4.2. Sample PCB Routing Scheme on 6 Layers for 0.5-mm 484-pin MBGA 1.3.4.3. Sample PCB Routing Scheme on 3 Layers for 0.5-mm 383-pin MBGA 1.3.4.4. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 301-pin MBGA 1.3.4.5. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 153-pin MBGA 1.3.4.6. Sample PCB Routing Scheme on 4 Layers for 0.5-mm 144-pin MBGA 1.3.4.7. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 256-pin and 100-pin MBGAs 1.3.4.8. Sample PCB Routing Scheme on 4 Layers for 0.4-mm 81-pin VBGA (also known as WLCSP) 1.3.4.9. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 68-pin MBGA 1.3.4.10. Sample PCB Routing Scheme on 2 Layers for 0.4-mm 36-pin VBGA (also known as WLCSP) 1.3.4.11. Sample PCB Routing Scheme on 3 Layers for 0.8-mm 324-pin UBGA 1.3.4.12. Sample PCB Routing Scheme on 3 Layers for 0.8-mm 169-pin UBGA
1. AN 114: Board Design Guidelines for Intel® Programmable Device Packages

1.3.4.7. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 256-pin and 100-pin MBGAs

In 2006, 0.5-mm pitch Micro FineLine BGA® (MBGA) packages is introduced in the MAX® II device family. The size and weight of these packages make them suitable for portable applications or any application that has board space and/or power constraints. The pin layout and the pin assignments have been designed so that the signals from solder pads can be routed in 2 layers using through-hole vias. Examples of layout schemes for routing on 2 layers is demonstrated in the following figures for the 100-pin and 256-pin MBGAs, respectively. This layout type is suitable for PCB thickness smaller than or equal to 1.5 mm. For PCB thickness greater than 1.5 mm, application of blind vias may be more suitable for escape routing. Additional MBGA packages have been added to the portfolio since 2006 and sample escape routing for these are shown in this section.

In this section, sample PCB routing schemes use VCCN and VSS. In the pin table, VCCN and VSS correspond to VCCIO and GND, respectively.

Figure 28. A Sample PCB Routing Scheme on 2 Layers for 0.5-mm 256-pin MBGA
Figure 29. A Sample PCB Routing Scheme on 2 Layers for 0.5-mm 100-pin MBGA
Level Two Title