AN 114: Board Design Guidelines for Intel Programmable Device Packages

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ID 683481
Date 5/27/2022
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Document Table of Contents
Document Table of Contents x
1. AN 114: Board Design Guidelines for Intel® Programmable Device Packages
1. AN 114: Board Design Guidelines for Intel® Programmable Device Packages x
1.1. Overview of BGA Packages 1.2. PCB Layout Terminology 1.3. PCB Layout for High-Density BGA Packages 1.4. Document Revision History for AN 114: Board Design Guidelines for Intel® Programmable Device Packages
1.2. PCB Layout Terminology x
1.2.1. Escape Routing 1.2.2. Multi-Layer PCBs 1.2.3. Vias 1.2.4. Via Capture Pad 1.2.5. Surface Land Pad 1.2.6. Stringer
1.2.5. Surface Land Pad x
1.2.5.1. Non Solder Mask Defined Pad 1.2.5.2. Solder Mask Defined Pad
1.3. PCB Layout for High-Density BGA Packages x
1.3.1. Surface Land Pad Dimension 1.3.2. Via Capture Pad Layout and Dimension 1.3.3. Signal Line Space and Trace Width 1.3.4. Number of PCB Layers
1.3.4. Number of PCB Layers x
1.3.4.1. Sample PCB Layout for 1.00-mm Flip-Chip BGA and 0.80-mm UBGA (BT Substrate) 1.3.4.2. Sample PCB Routing Scheme on 6 Layers for 0.5-mm 484-pin MBGA 1.3.4.3. Sample PCB Routing Scheme on 3 Layers for 0.5-mm 383-pin MBGA 1.3.4.4. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 301-pin MBGA 1.3.4.5. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 153-pin MBGA 1.3.4.6. Sample PCB Routing Scheme on 4 Layers for 0.5-mm 144-pin MBGA 1.3.4.7. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 256-pin and 100-pin MBGAs 1.3.4.8. Sample PCB Routing Scheme on 4 Layers for 0.4-mm 81-pin VBGA (also known as WLCSP) 1.3.4.9. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 68-pin MBGA 1.3.4.10. Sample PCB Routing Scheme on 2 Layers for 0.4-mm 36-pin VBGA (also known as WLCSP) 1.3.4.11. Sample PCB Routing Scheme on 3 Layers for 0.8-mm 324-pin UBGA 1.3.4.12. Sample PCB Routing Scheme on 3 Layers for 0.8-mm 169-pin UBGA
1. AN 114: Board Design Guidelines for Intel® Programmable Device Packages

1.3.4. Number of PCB Layers

In general, the number of PCB layers required to route signals is inversely proportional to the number of traces between vias (i.e., the more traces used, the fewer PCB layers required). You can estimate the number of layers your PCB requires by first determining:

  • Trace and space size
  • Number of traces routed between the via capture pads
  • Type of vias used

Using fewer I/O pins than the maximum can reduce the required number of layers. The via type selected can also reduce the number of layers required. To see how the via type can affect the required number of PCB layers, consider the sample layouts shown in the following sections.


Section Content
Sample PCB Layout for 1.00-mm Flip-Chip BGA and 0.80-mm UBGA (BT Substrate)
Sample PCB Routing Scheme on 6 Layers for 0.5-mm 484-pin MBGA
Sample PCB Routing Scheme on 3 Layers for 0.5-mm 383-pin MBGA
Sample PCB Routing Scheme on 2 Layers for 0.5-mm 301-pin MBGA
Sample PCB Routing Scheme on 2 Layers for 0.5-mm 153-pin MBGA
Sample PCB Routing Scheme on 4 Layers for 0.5-mm 144-pin MBGA
Sample PCB Routing Scheme on 2 Layers for 0.5-mm 256-pin and 100-pin MBGAs
Sample PCB Routing Scheme on 4 Layers for 0.4-mm 81-pin VBGA (also known as WLCSP)
Sample PCB Routing Scheme on 2 Layers for 0.5-mm 68-pin MBGA
Sample PCB Routing Scheme on 2 Layers for 0.4-mm 36-pin VBGA (also known as WLCSP)
Sample PCB Routing Scheme on 3 Layers for 0.8-mm 324-pin UBGA
Sample PCB Routing Scheme on 3 Layers for 0.8-mm 169-pin UBGA

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