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1. MAX® 10 Embedded Multiplier Block Overview
2. MAX® 10 Embedded Multipliers Features and Architecture
3. MAX® 10 Embedded Multipliers Implementation Guides
4. LPM_MULT (Multiplier) IP Core References for MAX® 10
5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10
6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10
7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10
8. MAX® 10 Embedded Multipliers User Guide Archives
9. Document Revision History for the MAX® 10 Embedded Multipliers User Guide
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2.1.3. Output Register
You can register the embedded multiplier output using output registers in either 18- or 36-bit sections. This depends on the operational mode of the multiplier. The following control signals are available for each output register in the embedded multiplier:
- Clock
- Clock enable
- Asynchronous clear
All input and output registers in a single embedded multiplier are fed by the same clock, clock enable, and asynchronous clear signals.