MAX® 10 Embedded Multipliers User Guide

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ID 683467
Date 3/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 Embedded Multiplier Block Overview 2. MAX® 10 Embedded Multipliers Features and Architecture 3. MAX® 10 Embedded Multipliers Implementation Guides 4. LPM_MULT (Multiplier) IP Core References for MAX® 10 5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10 6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10 7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10 8. MAX® 10 Embedded Multipliers User Guide Archives 9. Document Revision History for the MAX® 10 Embedded Multipliers User Guide
2. MAX® 10 Embedded Multipliers Features and Architecture x
2.1. Embedded Multipliers Architecture 2.2. Embedded Multipliers Operational Modes
2.1. Embedded Multipliers Architecture x
2.1.1. Input Register 2.1.2. Multiplier Stage 2.1.3. Output Register
2.2. Embedded Multipliers Operational Modes x
2.2.1. 18-Bit Multipliers 2.2.2. 9-Bit Multipliers
3. MAX® 10 Embedded Multipliers Implementation Guides x
3.1. Files Generated by IP Cores
3.1. Files Generated by IP Cores x
3.1.1. Verilog HDL Prototype Location 3.1.2. VHDL Component Declaration Location
4. LPM_MULT (Multiplier) IP Core References for MAX® 10 x
4.1. LPM_MULT Parameter Settings 4.2. Signals
5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10 x
5.1. ALTMULT_ACCUM Parameter Settings 5.2. ALTMULT_ACCUM Ports
6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10 x
6.1. ALTMULT_ADD Parameter Settings 6.2. ALTMULT_ADD Ports
7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10 x
7.1. ALTMULT_COMPLEX Parameter Settings 7.2. Signals
1. MAX® 10 Embedded Multiplier Block Overview
2. MAX® 10 Embedded Multipliers Features and Architecture
3. MAX® 10 Embedded Multipliers Implementation Guides
4. LPM_MULT (Multiplier) IP Core References for MAX® 10
5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10
6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10
7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10
8. MAX® 10 Embedded Multipliers User Guide Archives
9. Document Revision History for the MAX® 10 Embedded Multipliers User Guide

5.2. ALTMULT_ACCUM Ports

Table 13.  ALTMULT_ACCUM IP Core Input Ports
Port Name Required Description
accum_sload No

Causes the value on the accumulator feedback path to go to zero (0) or to accum_sload_upper_data when concatenated with 0. If the accumulator is adding and the accum_sload port is high, then the multiplier output is loaded into the accumulator. If the accumulator is subtracting, then the opposite (negative value) of the multiplier output is loaded into the accumulator.

aclr0 No The first asynchronous clear input. The aclr0 port is active high.
aclr1 No The second asynchronous clear input. The aclr1 port is active high.
aclr2 No The third asynchronous clear input. The aclr2 port is active high.
aclr3 No The fourth asynchronous clear input. The aclr3 port is active high.
addnsub No Controls the functionality of the adder. If the addnsub port is high, the adder performs an add function; if the addnsub port is low, the adder performs a subtract function.
clock0 No Specifies the first clock input, usable by any register in the IP core.
clock1 No Specifies the second clock input, usable by any register in the IP core.
clock2 No Specifies the third clock input, usable by any register in the IP core.
clock3 No Specifies the fourth clock input, usable by any register in the IP core.
dataa[] Yes Data input to the multiplier. The size of the input port depends on the WIDTH_A parameter value.
datab[] Yes Data input to the multiplier. The size of the input port depends on the WIDTH_B parameter value.
ena0 No Clock enable for the clock0 port.
ena1 No Clock enable for the clock1 port.
ena2 No Clock enable for the clock2 port.
ena3 No Clock enable for the clock3 port.
signa No Specifies the numerical representation of the dataa[] port. If the signa port is high, the multiplier treats the dataa[] port as signed two's complement. If the signa port is low, the multiplier treats the dataa[] port as an unsigned number.
signb No Specifies the numerical representation of the datab[] port. If the signb port is high, the multiplier treats the datab[] port as signed two's complement. If the signb port is low, the multiplier treats the datab[]port as an unsigned number.
Table 14.  ALTMULT_ACCUM IP Core Output Ports
Port Name Required Description
overflow No Overflow port for the accumulator.
result[] Yes Accumulator output port. The size of the output port depends on the WIDTH_RESULT parameter value.
scanouta[] No Output of the first shift register. The size of the output port depends on the WIDTH_A parameter value. When instantiating the ALTMULT_ACCUM IP core with the MegaWizard Plug-In Manager, the MegaWizard Plug-In Manager renames the scanouta[] port to shiftouta port.
scanoutb[] No Output of the second shift register. The size of the input port depends on the WIDTH_B parameter value. When instantiating the ALTMULT_ACCUM IP core with the MegaWizard Plug-In Manager, the MegaWizard Plug-In Manager renames the scanoutb[] port to shiftoutb port.
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