MAX® 10 Embedded Multipliers User Guide

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ID 683467
Date 3/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 Embedded Multiplier Block Overview 2. MAX® 10 Embedded Multipliers Features and Architecture 3. MAX® 10 Embedded Multipliers Implementation Guides 4. LPM_MULT (Multiplier) IP Core References for MAX® 10 5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10 6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10 7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10 8. MAX® 10 Embedded Multipliers User Guide Archives 9. Document Revision History for the MAX® 10 Embedded Multipliers User Guide
2. MAX® 10 Embedded Multipliers Features and Architecture x
2.1. Embedded Multipliers Architecture 2.2. Embedded Multipliers Operational Modes
2.1. Embedded Multipliers Architecture x
2.1.1. Input Register 2.1.2. Multiplier Stage 2.1.3. Output Register
2.2. Embedded Multipliers Operational Modes x
2.2.1. 18-Bit Multipliers 2.2.2. 9-Bit Multipliers
3. MAX® 10 Embedded Multipliers Implementation Guides x
3.1. Files Generated by IP Cores
3.1. Files Generated by IP Cores x
3.1.1. Verilog HDL Prototype Location 3.1.2. VHDL Component Declaration Location
4. LPM_MULT (Multiplier) IP Core References for MAX® 10 x
4.1. LPM_MULT Parameter Settings 4.2. Signals
5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10 x
5.1. ALTMULT_ACCUM Parameter Settings 5.2. ALTMULT_ACCUM Ports
6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10 x
6.1. ALTMULT_ADD Parameter Settings 6.2. ALTMULT_ADD Ports
7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10 x
7.1. ALTMULT_COMPLEX Parameter Settings 7.2. Signals
1. MAX® 10 Embedded Multiplier Block Overview
2. MAX® 10 Embedded Multipliers Features and Architecture
3. MAX® 10 Embedded Multipliers Implementation Guides
4. LPM_MULT (Multiplier) IP Core References for MAX® 10
5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10
6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10
7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10
8. MAX® 10 Embedded Multipliers User Guide Archives
9. Document Revision History for the MAX® 10 Embedded Multipliers User Guide

5.1. ALTMULT_ACCUM Parameter Settings

There are four groups of options: General, Extra Modes, Multipliers, and Accumulator.

Table 9.  ALTMULT_ACCUM Parameters - General This table lists the IP core parameters applicable to MAX® 10 devices.
GUI Parameter Parameter Condition Value Description
What is the number of multipliers? NUMBER_OF_MULTIPLIERS — 1 By default, only 1 multiplier is supported.
All multipliers have similar configurations — — On By default all multipliers have similar configurations
How wide should the A input buses be? WIDTH_A — 1–256 Specifies the width of A input buses.
How wide should the B input buses be? WIDTH_B — 1–256 Specifies the width of B input buses.
How wide should the ‘result’ output bus be? WIDTH_RESULT — 1–256 Specifies the width of ‘result’ output bus.
Create a 4th asynchronous clear input option — — On or Off Turn on this option if you want to create a 4th asynchronous clear input option.
Create an associated clock enable for each clock — — On or Off Turn on this option if you want to create an associated clock enable for each clock.
What is the representation format for A inputs? REPRESENTATION_A —
  • Signed
  • Unsigned
  • Variable
 Specifies the representation format for A inputs.
‘signa’ input controls the sign (1 signed/0 unsigned) PORT_SIGNA Input Representation > What is the representation format for A inputs? = Variable More Options High ‘signa’ input indicates signed and low ‘signa’ input indicates unsigned.
Register ‘signa’ input — Input Representation > More Options On or Off Turn on this option if you want to enable the register of ‘signa’ input
Add an extra pipeline register — Input Representation > More Options On or Off Turn on this option if you want to enable the extra pipeline register
Input Register > What is the source for clock input? SIGN_REG_A Input Representation > More Options Clock0–Clock3 Specifies the source for clock input.
Input Register > What is the source for asynchronous clear input? SIGN_ACLR_A Input Representation > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
Pipeline Register > What is the source for clock input? SIGN_PIPELINE_REG_A Input Representation > More Options Clock0–Clock3 Specifies the source for clock input.
Pipeline Register > What is the source for asynchronous clear input? SIGN_PIPELINE_ACLR_A Input Representation > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
What is the representation format for B inputs? REPRESENTATIONS_B —
  • Signed
  • Unsigned
  • Variable
 Specifies the representation format for B inputs.
‘signb’ input controls the sign (1 signed/0 unsigned) PORT_SIGNB Input Representation > What is the representation format for B inputs? = Variable More Options High ‘signb’ input indicates signed and low ‘signb’ input indicates unsigned.
Register ‘signb’ input — Input Representation > More Options On or Off Turn on this option if you want to enable the register of ‘signb’ input
Add an extra pipeline register — Input Representation > More Options On or Off Turn on this option if you want to enable the extra pipeline register
Input Register > What is the source for clock input? SIGN_REG_B Input Representation > More Options Clock0–Clock3 Specifies the source for clock input.
Input Register > What is the source for asynchronous clear input? SIGN_ACLR_B Input Representation > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
Pipeline Register > What is the source for clock input? SIGN_PIPELINE_REG_B Input Representation > More Options Clock0–Clock3 Specifies the source for clock input.
Pipeline Register > What is the source for asynchronous clear input? SIGN_PIPELINE_ACLR_B Input Representation > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
Table 10.  ALTMULT_ACCUM Parameters - Extra Modes
GUI Parameter Parameter Condition Value Description
Create a shiftout output from A input of the last multiplier — — On or Off Turn on this option to create a shiftout output from A input of the last multiplier.
Create a shiftout output from B input of the last multiplier — — On or Off Turn on this option to create a shiftout output from B input of the last multiplier.
Add extra register(s) at the output — — On By default, output register must be enabled for accumulator.
What is the source for clock input? OUTPUT_REG Outputs Configuration > More Options Clock0–Clock3 Specifies the clock signal for the registers on the outputs.
What is the source for asynchronous clear input? OUTPUT_ACLR Outputs Configuration > More Options
  • Aclr0–Aclr2
  • None
 Specifies the asynchronous clear signal for the registers on the outputs.
Add [] extra latency to the output — Outputs Configuration > More Options 0, 1, 2, 3, 4, 5, 6, 7, 8, or 12 Specifies the extra latency to add to the output.
Which multiplier-adder implementation should be used? DEDICATED_MULTIPLIER_CIRCUITRY —
  • Use the default implementation
  • Use dedicated multiplier circuitry (Not available for all families)
  • Use logic elements
 Specifies the multiplier-adder implementation.
Table 11.  ALTMULT_ACCUM Parameters - Multipliers This table lists the IP core parameters applicable to MAX® 10 devices.
GUI Parameter Parameter Condition Value Description
Register input A of the multiplier — — On or Off Turn on to enable register input A of the multiplier.
What is the source for clock input? INPUT_REG_A
  • Input Configuration > Register input A of the multiplier = On
  • Input Configuration > More Options
 Clock0–Clock3 Specifies the clock port for the dataa[] port.
What is the source for asynchronous clear input? INPUT_ACLR_A
  • Input Configuration > Register input A of the multiplier = On
  • Input Configuration > More Options
  • Aclr0–Aclr2
  • None
 Specifies the asynchronous clear port for the dataa[] port.
Register input B of the multiplier — — On or Off Turn on to enable register input B of the multiplier.
What is the source for clock input? INPUT_REG_B
  • Input Configuration > Register input B of the multiplier = On
  • Input Configuration > More Options
 Clock0–Clock3 Specifies the clock port for the datab[] port.
What is the source for asynchronous clear input? INPUT_ACLR_B
  • Input Configuration > Register input B of the multiplier = On
  • Input Configuration > More Options
  • Aclr0–Aclr2
  • None
 Specifies the asynchronous clear port for the datab[] port.
What is the input A of the multiplier connected to? — — Multiplier input By default, input A of the multiplier is always connected to the multiplier’s input.
What is the input B of the multiplier connected to? — — Multiplier input By default, input B of the multiplier is always connected to the multiplier’s input.
Register output of the multiplier — — On or Off Turn on to enable register output of the multiplier.
What is the source for clock input? MULTIPLIER_REG
  • Output Configuration > Register output of the multiplier = On
  • Output Configuration > More Options
 Clock0–Clock3 Specifies the clock signal for the register that immediately follows the multiplier.
What is the source for asynchronous clear input? MULTIPLIER_ACLR
  • Output Configuration > Register output of the multiplier = On
  • Output Configuration > More Options
  • Aclr0–Aclr2
  • None
 Specifies the asynchronous clear signal of the register that follows the corresponding multiplier.
Table 12.  ALTMULT_ACCUM Parameters - Accumulator This table lists the IP core parameters applicable to MAX® 10 devices.
GUI Parameter Parameter Condition Value Description
Create an ‘accum_sload’ input port — — On or off Dynamically specifies whether the accumulator value is constant. If the accum_sload port is high, then the multiplier output is loaded into the accumulator.
Register ‘accum_sload’ input —
  • Accumulator > Create an ‘accum_sload’ input port = On
  • Accumulator > More Options
 On or off Turn on to enable register ‘accum_sload’ input.
Add an extra pipeline register —
  • Accumulator > Create an ‘accum_sload’ input port = On
  • Accumulator > More Options
 On or off Turn on this option if you want to enable the extra pipeline register
Input Register > What is the source for clock input? ACCUM_SLOAD_REG
  • Accumulator > Create an ‘accum_sload’ input port = On
  • Accumulator > More Options
 Clock0–Clock3 Specifies the clock signal for the accum_sload port.
Input Register > What is the source for asynchronous clear input? ACCUM_SLOAD_ACLR
  • Accumulator > Create an ‘accum_sload’ input port = On
  • Accumulator > More Options
  • Aclr0–Aclr2
  • None
 Specifies the asynchronous clear source for the first register on the accum_sload input.
Pipeline Register > What is the source for clock input? ACCUM_SLOAD_PIPELINE_REG
  • • Accumulator > Create an ‘accum_sload’ input port = On
  • Accumulator > More Options
 Clock0–Clock3 Specifies the source for clock input.
Pipeline Register > What is the source for asynchronous clear input? ACCUM_SLOAD_PIPELINE_ACLR
  • Accumulator > Create an ‘accum_soad’ input port = On
  • Accumulator > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
Create an ‘overflow’ output port — — On or Off Overflow port for the accumulator
Add [] extra latency to the multiplier output EXTRA_MULTIPLIER_LATENCY — 0, 1, 2, 3, 4, 5, 6, 7, 8, or 12 Specifies the number of clock cycles of latency for the multiplier portion of the DSP block. If the MULTIPLIER_REG parameter is specified, then the specified clock port is used to add the latency.
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