MAX® 10 Embedded Multipliers User Guide

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ID 683467
Date 3/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 Embedded Multiplier Block Overview 2. MAX® 10 Embedded Multipliers Features and Architecture 3. MAX® 10 Embedded Multipliers Implementation Guides 4. LPM_MULT (Multiplier) IP Core References for MAX® 10 5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10 6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10 7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10 8. MAX® 10 Embedded Multipliers User Guide Archives 9. Document Revision History for the MAX® 10 Embedded Multipliers User Guide
2. MAX® 10 Embedded Multipliers Features and Architecture x
2.1. Embedded Multipliers Architecture 2.2. Embedded Multipliers Operational Modes
2.1. Embedded Multipliers Architecture x
2.1.1. Input Register 2.1.2. Multiplier Stage 2.1.3. Output Register
2.2. Embedded Multipliers Operational Modes x
2.2.1. 18-Bit Multipliers 2.2.2. 9-Bit Multipliers
3. MAX® 10 Embedded Multipliers Implementation Guides x
3.1. Files Generated by IP Cores
3.1. Files Generated by IP Cores x
3.1.1. Verilog HDL Prototype Location 3.1.2. VHDL Component Declaration Location
4. LPM_MULT (Multiplier) IP Core References for MAX® 10 x
4.1. LPM_MULT Parameter Settings 4.2. Signals
5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10 x
5.1. ALTMULT_ACCUM Parameter Settings 5.2. ALTMULT_ACCUM Ports
6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10 x
6.1. ALTMULT_ADD Parameter Settings 6.2. ALTMULT_ADD Ports
7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10 x
7.1. ALTMULT_COMPLEX Parameter Settings 7.2. Signals
1. MAX® 10 Embedded Multiplier Block Overview
2. MAX® 10 Embedded Multipliers Features and Architecture
3. MAX® 10 Embedded Multipliers Implementation Guides
4. LPM_MULT (Multiplier) IP Core References for MAX® 10
5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10
6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10
7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10
8. MAX® 10 Embedded Multipliers User Guide Archives
9. Document Revision History for the MAX® 10 Embedded Multipliers User Guide

4.1. LPM_MULT Parameter Settings

There are three groups of options: General, General2, and Pipeling.

Table 4.  LPM_MULT Parameters - General This table lists the IP core parameters applicable to MAX® 10 devices.
GUI Parameter Parameter Condition Value Description
Multiplier configuration — —
  • Multiply ‘dataa’ input by ‘datab’ input
  • Multiply ‘dataa’ input by itself (squaring operation)
Specifies the multiplier configuration.
How wide should the ‘dataa’ input be? LPM_WIDTHA — 1–256 Specifies the width of the dataa[] port.
How wide should the ‘datab’ input be? LPM_WIDTHB — 1–256 Specifies the width of the datab[] port.
How should the width of the ‘result’ output be determined? LPM_WIDTHP —
  • Automatically calculate the width
  • Restrict the width to [] bits
 Specifies how the result width is determined.

How should the width of the ‘result’ output be determined? >

Restrict the width to [] bits

 LPM_WIDTHP

How should the width of the ‘result’ output be determined? >

Restrict the width to [] bits = On

 1–256 You can set the result width.
Table 5.  LPM_MULT Parameters - General2 This table lists the IP core parameters applicable to MAX® 10 devices.
GUI Parameter Parameter Condition Value Description
Does the ‘datab’ input bus have a constant value? — —
  • No
  • Yes, the value is []
 You can specify the constant value of the ‘datab’ input bus, if any.
Which type of multiplication do you want? LPM_REPRESENTATION —
  • Unsigned
  • Signed
 Specifies the type of multiplication performed.
Which multiplier implementation should be used? DEDICATED_MULTIPLIER_CIRCUITRY —
  • Use default implementation
  • Use the dedicated multiplier circuitry (Not available for all families)
  • Use logic elements
 Specifies the multiplier implementation.
Table 6.  LPM_MULT Parameters - Pipeling This table lists the IP core parameters applicable to MAX® 10 devices.
GUI Parameter Parameter Condition Value Description
Do you want to pipeline the function? LPM_PIPELINE —
  • No
  • Yes, I want output latency of [] clock cycles
 You can add extra latency to the outputs, if any.
Create an ‘aclr’ asynchronous clear port — Do you want to pipeline the function? = Yes, I want output latency of [] clock cycles On or off Specifies asynchronous clear for the complex multiplier. Clears the function asynchronously when aclr port is asserted high.
Create a ‘clken’ clock enable clock — Do you want to pipeline the function? = Yes, I want output latency of [] clock cycles On or off Specifies active high clock enable for the clock port of the complex multiplier
What type of optimization do you want? MAXIMIZE_SPEED —
  • Default
  • Speed
  • Area
 You can specify if the type of optimization is determined by Quartus® Prime, speed, or area.
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