4. Considering Design Security
Intel provide this design as a showcase for the Intel FPGA IP and do not intend it for use in production or deployed systems. Several features of the design may not meet customer security requirements. You should conduct a security review of your final design to ensure it meets your security goals.
Not all precautions apply to all designs or IP.
- Remove the JTAG interface from your designs.
- To guarantee video data integrity, restrict access to memory allocated to the frame buffer.
- Control access to areas of memory to prevent unauthorised transactions or corruption by other IP in the design.
- Ensure that you correctly configure the IP via the I²C interface and that the input video is valid.
- Protect the bitstreams for your design using the security features built-in to Intel Quartus Prime.
- Enable a password for the design’s ARM processor.
- Protect access to your design through development kit ports.
- Restrict debugging access by tools such as Signal Tap.
- Encrypt information on SD cards, FPGA bitstreams, and within DDR memory devices.
- Apply security features to the video data is storage.
- Consider using an HDCP encryption scheme.
- Consider the boot sequence and boot security aspects of your own design.
- Implement Intel’s FPGA bitstream encryption technology to further protect the FPGA design content of your products. For information on FPGA bitstream encryption technology, refer to Using the Design Security Features in Intel FPGAs.