AN 776: UHD HDMI 2.0 Video Format Conversion Design Example

Download PDF
ID 683465
Date 4/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the UHD HDMI 2.0 Video Format Conversion Design Example 2. UHD HDMI 2.0 Video Format Conversion Design Example Getting Started 3. UHD HDMI 2.0 Video Format Conversion Design Example Functional Description 4. Considering Design Security 5. UHD HDMI 2.0 Video Format Conversion Design Example Document Revision History A. HDMI RX Interface Register Map B. HDMI TX Interface Register Map
1. About the UHD HDMI 2.0 Video Format Conversion Design Example x
1.1. UHD HDMI 2.0 Video Format Conversion Design Example Features
2. UHD HDMI 2.0 Video Format Conversion Design Example Getting Started x
2.1. Hardware and Software Requirements for the UHD HDMI 2.0 Video Format Conversion Design Example 2.2. Downloading and Installing the UHD HDMI 2.0 Video Format Conversion Design Example 2.3. Setting up the Intel® Arria® 10 FPGA development board 2.4. Compiling the UHD HDMI 2.0 Video Format Conversion Design Example 2.5. Compiling the UHD HDMI 2.0 Video Format Conversion Design Example with the Nios II Software Tools for Eclipse 2.6. Running the UHD HDMI 2.0 Video Format Conversion Design Example on the Hardware
2.2. Downloading and Installing the UHD HDMI 2.0 Video Format Conversion Design Example x
2.2.1. Installation Files for the UHD HDMI 2.0 Video Format Conversion Design Example
2.3. Setting up the Intel® Arria® 10 FPGA development board x
2.3.1. Board Status Lights, DIP Switches, and Pushbuttons
3. UHD HDMI 2.0 Video Format Conversion Design Example Functional Description x
3.1. Software Description
1. About the UHD HDMI 2.0 Video Format Conversion Design Example
2. UHD HDMI 2.0 Video Format Conversion Design Example Getting Started
3. UHD HDMI 2.0 Video Format Conversion Design Example Functional Description
4. Considering Design Security
5. UHD HDMI 2.0 Video Format Conversion Design Example Document Revision History
A. HDMI RX Interface Register Map
B. HDMI TX Interface Register Map

2.4. Compiling the UHD HDMI 2.0 Video Format Conversion Design Example

Intel also provides a precompiled board programming file precompiled.sof as part of the project file in the master_image directory, so you can run the design without running a full compilation.
The steps show you how to compile the design, but the Intel Quartus project includes a Tcl script that automates steps 2 to 6, so you can choose to skip those step. Intel includes all the steps for compiling the design so you understand how the design is assembled.
  1. In the Intel® Quartus® Prime software, open the project file top.qpf.
  2. 2. Click File > Open and select ip/hdmi_subsys/hdmi_subsys.ip.
    The paramerer parameter editor GUI for the HDMI IP opens, showing the parameters for the HDMI instance in the design.
  3. Click Generate Example Design (not Generate).
  4. When the generation completes, close the parameter editor.
  5. Click Tools > Platform Designer to open Platform Designer.
    1. Select udx10_hdmi.qsys for the Platform Designer system option and click Open
    2. Review the video processing pipeline.
    3. To generate the system, click Generate HDL…
    4. In the Generation window, turn on Clear output directories for selected generation targets.
    5. Click Generate.
  6. In a terminal, navigate to software/script and run the shell script build_sw.sh.
    The software builds the Nios II software for the design, creating both the vip_control.elf file that you can download to the board at runtime, and a .hex file that compiles into the board programming .sof file.
  7. Click Processing > Start Compilation.
    The compilation creates the top.sof file in the output_files directory.
Related Information
Level Two Title