Intel® Quartus® Prime Pro Edition User Guide: Getting Started

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ID 683463
Date 6/20/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Introduction to Intel® Quartus® Prime Pro Edition 3. Managing Intel® Quartus® Prime Projects 4. Design Planning 5. Introduction to Intel® FPGA IP Cores 6. Migrating to Intel® Quartus® Prime Pro Edition 7. Document Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Introduction to Intel® Quartus® Prime Pro Edition x
2.1. FPGA Basic Design Prerequisites 2.2. Selecting an Intel® Quartus® Prime Software Edition 2.3. Experiment with a Design Example 2.4. Introduction to Intel® Quartus® Prime Pro Edition Revision History
3. Managing Intel® Quartus® Prime Projects x
3.1. Viewing Basic Project Information 3.2. Intel® Quartus® Prime Project Contents 3.3. Managing Project Settings 3.4. Managing Logic Design Files 3.5. Managing Timing Constraints 3.6. Integrating Other EDA Tools 3.7. Exporting Compilation Results 3.8. Migrating Projects Across Operating Systems 3.9. Archiving Projects 3.10. Command-Line Interface 3.11. Managing Projects Revision History
3.1. Viewing Basic Project Information x
3.1.1. Using the Compilation Dashboard 3.1.2. Viewing Project Reports 3.1.3. Viewing Project Messages
3.1.3. Viewing Project Messages x
3.1.3.1. Viewing Synthesis Warning Messages 3.1.3.2. Suppressing Message Display 3.1.3.3. Promoting Critical Warnings to Errors
3.2. Intel® Quartus® Prime Project Contents x
3.2.1. Project File Best Practices
3.3. Managing Project Settings x
3.3.1. Specifying the Target Device or Board 3.3.2. Optimizing Project Settings
3.3.2. Optimizing Project Settings x
3.3.2.1. Optimize Settings with Design Space Explorer II 3.3.2.2. Optimize Settings with Project Revisions 3.3.2.3. Back-Annotate Optimized Assignments
3.4. Managing Logic Design Files x
3.4.1. Including Design Libraries 3.4.2. Creating a Project Copy
3.7. Exporting Compilation Results x
3.7.1. Exporting a Version-Compatible Compilation Database 3.7.2. Importing a Version-Compatible Compilation Database 3.7.3. Creating a Design Partition 3.7.4. Exporting a Design Partition 3.7.5. Reusing a Design Partition 3.7.6. Viewing Quartus Database File Information 3.7.7. Clearing Compilation Results
3.7.6. Viewing Quartus Database File Information x
3.7.6.1. QDB File Attribute Types
3.8. Migrating Projects Across Operating Systems x
3.8.1. Migrating Design Files and Libraries 3.8.2. Design Library Migration Guidelines
3.8.1. Migrating Design Files and Libraries x
3.8.1.1. Use Relative Paths
3.9. Archiving Projects x
3.9.1. Manually Adding Files To Archives 3.9.2. Archiving Projects for Service Requests 3.9.3. Archiving Projects for External Revision Control 3.9.4. Creating Database-Only Archives
3.9.3. Archiving Projects for External Revision Control x
3.9.3.1. Project Files to Include In External Revision Control
3.10. Command-Line Interface x
3.10.1. Project Revision Commands 3.10.2. Project Archive Commands 3.10.3. Project Database Commands
3.10.3. Project Database Commands x
3.10.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
4. Design Planning x
4.1. Design Planning 4.2. Create a Design Specification and Test Plan 4.3. Plan for the Target Device 4.4. Plan for Intellectual Property Cores 4.5. Plan for Standard Interfaces 4.6. Plan for Device Programming 4.7. Plan for Device Power Consumption 4.8. Plan for Interface I/O Pins 4.9. Plan for other EDA Tools 4.10. Plan for On-Chip Debugging Tools 4.11. Plan HDL Coding Styles 4.12. Plan for Hierarchical and Team-Based Designs 4.13. Design Planning Revision History
4.3. Plan for the Target Device x
4.3.1. Device Migration Planning
4.9. Plan for other EDA Tools x
4.9.1. Third-Party Synthesis Tools 4.9.2. Third-Party Simulation Tools
4.11. Plan HDL Coding Styles x
4.11.1. Design Recommendations 4.11.2. Recommended HDL Coding Styles 4.11.3. Managing Metastability
4.12. Plan for Hierarchical and Team-Based Designs x
4.12.1. Flat Compilation without Design Partitions
5. Introduction to Intel® FPGA IP Cores x
5.1. IP Catalog and Parameter Editor 5.2. Installing and Licensing Intel® FPGA IP Cores 5.3. IP General Settings 5.4. Adding IP to IP Catalog 5.5. Best Practices for Intel® FPGA IP 5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 5.7. Modifying an IP Variation 5.8. Upgrading IP Cores 5.9. Simulating Intel® FPGA IP Cores 5.10. Generating Simulation Files for Platform Designer Systems and IP Variants 5.11. Synthesizing IP Cores in Other EDA Tools 5.12. Instantiating IP Cores in HDL 5.13. Support for the IEEE 1735 Encryption Standard 5.14. Introduction to Intel FPGA IP Cores Revision History
5.1. IP Catalog and Parameter Editor x
5.1.1. The Parameter Editor
5.2. Installing and Licensing Intel® FPGA IP Cores x
5.2.1. Intel® FPGA IP Evaluation Mode
5.2.1. Intel® FPGA IP Evaluation Mode x
5.2.1.1. Intel FPGA IP Versioning 5.2.1.2. Checking the IP License Status
5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
5.6.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.6.2. Scripting IP Core Generation
5.8. Upgrading IP Cores x
5.8.1. Upgrading IP Cores at Command-Line 5.8.2. Migrating IP Cores to a Different Device 5.8.3. Troubleshooting IP or Platform Designer System Upgrade
5.9. Simulating Intel® FPGA IP Cores x
5.9.1. Generating IP Simulation Files 5.9.2. Scripting IP Simulation
5.9.2. Scripting IP Simulation x
5.9.2.1. Generating a Combined Simulator Setup Script
5.12. Instantiating IP Cores in HDL x
5.12.1. Example Top-Level Verilog HDL Module 5.12.2. Example Top-Level VHDL Module
6. Migrating to Intel® Quartus® Prime Pro Edition x
6.1. Keep Pro Edition Project Files Separate 6.2. Upgrade Project Assignments and Constraints 6.3. Upgrade IP Cores and Platform Designer Systems 6.4. Upgrade Non-Compliant Design RTL 6.5. Migrating to Intel® Quartus® Prime Pro Edition Revision History
6.2. Upgrade Project Assignments and Constraints x
6.2.1. Modify Entity Name Assignments 6.2.2. Resolve Timing Constraint Entity Names 6.2.3. Verify Generated Node Name Assignments 6.2.4. Replace Logic Lock (Standard) Regions 6.2.5. Modify Signal Tap Logic Analyzer Files 6.2.6. Remove References to .qip Files 6.2.7. Remove Unsupported Feature Assignments
6.2.4. Replace Logic Lock (Standard) Regions x
6.2.4.1. Logic Lock Region Assignment Examples
6.4. Upgrade Non-Compliant Design RTL x
6.4.1. Verify Verilog Compilation Unit 6.4.2. Update Entity Auto-Discovery 6.4.3. Ensure Distinct VHDL Namespace for Each Library 6.4.4. Remove Unsupported Parameter Passing 6.4.5. Remove Unsized Constant from WYSIWYG Instantiation 6.4.6. Remove Non-Standard Pragmas 6.4.7. Declare Objects Before Initial Values 6.4.8. Confine SystemVerilog Features to SystemVerilog Files 6.4.9. Avoid Assignment Mixing in Always Blocks 6.4.10. Avoid Unconnected, Non-Existent Ports 6.4.11. Avoid Illegal Parameter Ranges 6.4.12. Update Verilog HDL and VHDL Type Mapping
6.4.1. Verify Verilog Compilation Unit x
6.4.1.1. Verilog HDL Configuration Instantiation
1. Answers to Top FAQs
2. Introduction to Intel® Quartus® Prime Pro Edition
3. Managing Intel® Quartus® Prime Projects
4. Design Planning
5. Introduction to Intel® FPGA IP Cores
6. Migrating to Intel® Quartus® Prime Pro Edition
7. Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides

5.8.2. Migrating IP Cores to a Different Device

Migrate an Intel® FPGA IP variation when you want to target a different (often newer) device. Most Intel® FPGA IP cores support automatic migration. Some IP cores require manual IP regeneration for migration. A few IP cores do not support device migration, requiring you to replace them in the project. The Upgrade IP Components dialog box identifies the migration support level for each IP core in the design.
  1. To display the IP cores that require migration, click Project > Upgrade IP Components. The Description field provides migration instructions and version differences.
  2. To migrate one or more IP cores that support automatic upgrade, ensure that the Auto Upgrade option is turned on for the IP cores, and click Perform Automatic Upgrade. The Status and Version columns update when upgrade is complete.
  3. To migrate an IP core that does not support automatic upgrade, double-click the IP core name, and click OK. The parameter editor appears. If the parameter editor specifies a Currently selected device family, turn off Match project/default, and then select the new target device family.
  4. Click Generate HDL, and confirm the Synthesis and Simulation file options. Verilog HDL is the default output file format. If you specify VHDL as the output format, select VHDL to retain the original output format.
  5. Click Finish to complete migration of the IP core. Click OK if the software prompts you to overwrite IP core files. The Device Family column displays the new target device name when migration is complete.
  6. To ensure correctness, review the latest parameters in the parameter editor or generated HDL.
    Note: IP migration may change ports, parameters, or functionality of the IP variation. These changes may require you to modify your design or to re-parameterize your IP variant. During migration, the IP variation's HDL generates into a library that is different from the original output location of the IP core. Update any assignments that reference outdated locations. If a symbol in a supporting Block Design File schematic represents your upgraded IP core, replace the symbol with the newly generated <my_ip> .bsf. Migration of some IP cores requires installed support for the original and migration device families.
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