5. Solutions Comparison
Solution | Setup Relationship | Setup Slack | Timing Path | Advantages | |
---|---|---|---|---|---|
From | To | ||||
Falling edge clock data capturing | Full cycle latch (4 ns) |
1.814 ns |
DDIO IN pin | FPGA core register |
|
Half-rate transfer mode | Half cycle latch (2 ns) |
1.582 ns |
FR DDIO IN pin | HR DDIO IN registers in GPIO Intel® FPGA IP |
|
Half cycle latch (4 ns) |
1.617 ns |
HR DDIO IN registers in GPIO Intel® FPGA IP | FPGA core register |