AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex® 7 F-Series and I-Series Devices

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ID 683457
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Design Examples Requirements 3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode 4. Using GPIO Intel® FPGA IP in Half-Rate Mode 5. Solutions Comparison 6. Document Revision History for AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex® 7 F-Series and I-Series Devices
1. Overview x
1.1. GPIO Intel® FPGA IP Architecture 1.2. Input Data Path Timing Violations
3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode x
3.14.1. Design Example Walkthrough3.14.1. Design Example Walkthrough
4. Using GPIO Intel® FPGA IP in Half-Rate Mode x
3.14.1. Design Example Walkthrough3.14.1. Design Example Walkthrough
1. Overview
2. Design Examples Requirements
3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode
4. Using GPIO Intel® FPGA IP in Half-Rate Mode
5. Solutions Comparison
6. Document Revision History for AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex® 7 F-Series and I-Series Devices

2. Design Examples Requirements

Software Requirements

There are three design example revisions described in this document:
  • top—original design example with setup timing violation.
  • top_w1—design example using falling edge clock latching solution.
  • top_w2—design example using half-rate transfer mode solution.

All three design examples were created using the Intel Agilex® 7 F-Series AGFA014R243E3V device in the Intel® Quartus® Prime Pro Edition software version 23.3.

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