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1. Overview
2. Design Examples Requirements
3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode
4. Using GPIO Intel® FPGA IP in Half-Rate Mode
5. Solutions Comparison
6. Document Revision History for AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel Agilex® 7 F-Series and I-Series Devices
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3.14.1. Design Example Walkthrough3.14.1. Design Example Walkthrough
To view the design connections and setup timing for the design example, follow these steps:
- Download the top.par design example from the Intel® FPGA Design Store and restore the design using the Intel® Quartus® Prime Pro Edition software version 23.3.
- At the Intel® Quartus® Prime menu, click Projects > Revisions and select the top_w1 revision.
- To view the design connections, at the Intel® Quartus® Prime menu, click Processing > Start > Start Analysis & Synthesis. Once completed, click Tools > Netlist Viewers > RTL Analyzer (Elaborated).
- From the Intel® Quartus® Prime menu, select Processing > Start Compilation to compile the project.
You must compile the design to view the setup timing for the design.Once the compilation completes, the Timing Analyzer window displays.
- From the Timing Analyzer menu, select Reports > Custom Reports > Report Timing.
- In the Report Timing window, click OK to display the timing report for all paths.
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