1.2. Input Data Path Timing Violations
The design example shows the connections of the GPIO Intel® FPGA IP input data pins assigned to PIN CT57 in the top I/O sub-bank. The DDIO IN pins are connected to the FPGA core registers and the registers are using a rising edge clock for data sampling. The GPIO Intel® FPGA IP in this design example is set to full-rate data transfer with a clock frequency of 250 MHz. The clock is provided by outclk0.
Figure 3. Block Diagram of Full-Rate Data Transfer from DDIO IN to FPGA Core
The following figure shows setup violation from the DDIO IN pins to the FPGA core registers. The latch clock occurs at half-cycle of the launch clock with only 2 ns setup relationship. However, the data arrival time is longer than the data required time.
Figure 4. Setup Violation Timing Waveform
To resolve this violation, you can use one of the following solutions:
- Using a falling edge clock for capturing data in the full-rate transfer mode. This solution allows your design to operate in the maximum GPIO clock frequency but requires changes to the clock in user logic.
- Using GPIO Intel® FPGA IP in half-rate transfer mode. This solution operates in a slower clock frequency without changing the user logic clock.