AN-785: Altera JESD204B IP Core and ADI AD9162 Hardware Checkout Report

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ID 683452
Date 12/06/2016
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Core and AD9162 Hardware Checkout Report
1. JESD204B IP Core and AD9162 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transceiver Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B IP Core and AD9162 Hardware Checkout Report

1.3.1. Transmitter Data Link Layer

This test area covers the test cases for code group synchronization (CGS) and initial lane alignment sequence.

On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The SignalTap II Logic Analyzer tool monitors the transmitter data link layer operation.

Level Two Title